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71.发明授权公开(公告)号：US09811273B1
公开(公告)日：2017-11-07
申请号：US14580833
申请日：2014-12-23
Applicant: CADENCE DESIGN SYSTEMS, INC.
Inventor： Sandeep Brahmadathan
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1068 , G06F2206/1014 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2207/2254
Abstract: The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.
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公开(公告)号：US20170309350A1
公开(公告)日：2017-10-26
申请号：US15649394
申请日：2017-07-13
Applicant: Silicon Motion, Inc.
Inventor： Ching-Ke Chen , Po-Sheng Chou , Yang-Chih Shen
CPC classification number: G11C29/52 , G06F11/1068 , G06F11/1076 , G06F11/108 , G11C2029/0411
Abstract: An exemplary embodiment provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.
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公开(公告)号：US20170308299A1
公开(公告)日：2017-10-26
申请号：US15398409
申请日：2017-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-UHN CHA , HOI-JU CHUNG , YE-SIN RYU , SEONG-JIN CHO
CPC classification number: G11C29/52 , G06F11/1048 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C29/70 , G11C2029/0411 , H03M13/13
Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.
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公开(公告)号：US20170300377A1
公开(公告)日：2017-10-19
申请号：US15099675
申请日：2016-04-15
Applicant: Micron Technology, Inc.
Inventor： Mustafa N. Kaynak , Patrick R. Khayat , Sivagnanam Parthasarathy
CPC classification number: G11C16/26 , G06F11/1012 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1111 , H03M13/13 , H03M13/3738 , H03M13/45
Abstract: The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.
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公开(公告)号：US20170300246A1
公开(公告)日：2017-10-19
申请号：US15099018
申请日：2016-04-14
Applicant: SanDisk Technologies Inc.
Inventor： Eliyahu Michaeli
CPC classification number: G06F3/0619 , G06F3/065 , G06F3/0653 , G06F3/0679 , G06F3/0688 , G06F11/1004 , G06F11/1072 , G06F11/1402 , G06F12/0246 , G06F2212/7201 , G11C29/52 , G11C29/765 , G11C2029/0411
Abstract: A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to determining that there is no error in the logical-to-physical map, store the logical-to-physical map in the non-volatile memory; and in response to determining that there is an error in an entry in the logical-to-physical map, attempt to recover the entry from a location in the storage system before storing the logical-to-physical map in the non-volatile memory. Other embodiments are provided.
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Patent Agency Ranking
公开(公告)号：US09785501B2
公开(公告)日：2017-10-10
申请号：US14182567
申请日：2014-02-18
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Idan Alrod , Eran Sharon
CPC classification number: G06F11/1072 , G06F11/076 , G06F2212/403 , G11C11/5642 , G11C29/52 , G11C2029/0411 , G11C2211/5621
Abstract: A data storage device includes a non-volatile memory and a controller. A method includes writing a first logical page to a physical page of the non-volatile memory. In response to a multistate error indication satisfying a threshold, the method further includes rewriting the first logical page at the non-volatile memory. The multistate error indication is determined based on the first logical page.
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公开(公告)号：US09778976B2
公开(公告)日：2017-10-03
申请号：US14982049
申请日：2015-12-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yasuhiko Takemura
CPC classification number: G06F11/1004 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C11/405 , G11C16/0416 , G11C16/0433 , G11C16/045 , G11C29/04 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.
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公开(公告)号：US09772901B2
公开(公告)日：2017-09-26
申请号：US14707471
申请日：2015-05-08
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： George P. Hoekstra , Ravindraraj Ramaraju
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0679 , G06F11/0766 , G06F11/1048 , G11C11/56 , G11C11/5642 , G11C16/3418 , G11C29/028 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0411
Abstract: A method and system are provided for error correction in a memory. Error correction code (ECC) for data stored in a portion of the memory is enabled. A location and number of errors for the portion of the memory is then stored. It is determined if the number of errors exceeds a predetermined number of errors. If the number of errors exceeds the predetermined number, then the data stored in the portion of the memory is refreshed. If refreshing does not correct the errors, then a different ECC may be used.
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公开(公告)号：US20170269998A1
公开(公告)日：2017-09-21
申请号：US15377518
申请日：2016-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung SUNWOO
CPC classification number: G06F11/1072 , G06F11/1044 , G06F11/1068 , G11C29/52 , G11C2029/0411
Abstract: A method of operating a non-volatile memory device, includes, storing sensed data in a page buffer circuit by sensing data stored in a source page of a memory cell array, outputting the sensed data from the page buffer circuit, performing error correction code (ECC) decoding of the sensed data output from the page buffer circuit, storing the decoded data in the page buffer circuit, and providing de-randomized data to an external device as read data by performing de-randomizing of the decoded data output from the page buffer circuit using seed values corresponding to the source page.
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公开(公告)号：US20170269994A1
公开(公告)日：2017-09-21
申请号：US15076409
申请日：2016-03-21
Applicant: NandEXT S.r.l.
Inventor： Margherita Maffeis
CPC classification number: G11C29/52 , G06F11/1012 , G11C7/04 , G11C11/5642 , G11C16/349 , G11C2029/0409 , G11C2029/0411 , G11C2211/5644 , H03M13/1105 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/458 , H03M13/6325
Abstract: A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises determining a reliability indication indicative of a reliability of the read bits, and iterating the following sequence of steps: soft decoding the read bits based on said reliability indication in order to obtain said information bits, determining at least one among a time indication indicative of a time elapsed since a last writing of the memory cells and a temperature indication indicative of a temperature of the memory cells, and applying at least one among said time indication and said temperature indication to said reliability indication. A corresponding solid state drive is also proposed.
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