公开(公告)号：US08995180B2

公开(公告)日：2015-03-31

申请号：US13689105

申请日：2012-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sergiy Romanovskyy

IPC: G11C11/16 ,  G11C11/56

CPC classification number: H01L43/08 ,  G11C11/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C13/004 ,  G11C13/0069 ,  H01L43/02

Abstract: A MRAM bit cell including a first magnetic tunnel junction (MTJ) connected to a first data line and a second MTJ connected to a second data line. The MRAM bit cell further includes a first transistor having a first terminal connected to the first MTJ and a second terminal connected to the second MTJ. The MRAM bit cell further includes a second transistor having a first terminal connected to a driving line and a second terminal connected to the first MTJ. The MRAM bit cell further includes a third transistor having a first terminal connected to the driving line and a second terminal connected to the second MTJ. A method of using the MRAM bit cell is also described.

Abstract translation: MRAM位单元包括连接到第一数据线的第一磁性隧道结（MTJ）和连接到第二数据线的第二MTJ。 MRAM位单元还包括具有连接到第一MTJ的第一端子和连接到第二MTJ的第二端子的第一晶体管。 MRAM位单元还包括第二晶体管，其具有连接到驱动线的第一端子和连接到第一MTJ的第二端子。 MRAM位单元还包括第三晶体管，其具有连接到驱动线的第一端子和连接到第二MTJ的第二端子。 还描述了使用MRAM位单元的方法。

公开(公告)号：US08947922B2

公开(公告)日：2015-02-03

申请号：US14245821

申请日：2014-04-04

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  H01L43/02

Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.

Abstract translation: 具有使用MTJ的磁状态读取的磁性隧道结（MTJ）的磁性随机存取存储器（MRAM）阵列，通过在其上施加电流读取MTJ。 此外，MRAM阵列具有参考MTJ，耦合到MTJ的读出放大器和参考MTJ，读出放大器可用于在确定MTJ的状态时将MTJ的电压与参考MTJ进行比较; 在第一端耦合到读出放大器并在第二端接地的第一电容器; 以及第二电容器，其在第一端处耦合到所述读出放大器并在第二端接地，所述第一电容器存储所述第一电容器，其中当读取所述MTJ时，将短电压脉冲施加到所述第一和第二电容器的每一个的第一端，从而 使电流通过MTJ在那里通过一小段时间间隔，从而避免对MTJ的读取干扰。

公开(公告)号：US20150023096A1

公开(公告)日：2015-01-22

申请号：US13442829

申请日：2012-04-09

Applicant: Jannier Maximo Roiz Wilson

Inventor： Jannier Maximo Roiz Wilson

IPC: G11C11/15

CPC classification number: G11C11/00 ,  G11C11/15

Abstract: A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled.

Abstract translation: 提供磁存储单元。 该电池包括第一和第二自由层; 以及分离第一和第二自由层的中间层，其中第一和第二自由层被静磁耦合。

公开(公告)号：US20140361303A1

公开(公告)日：2014-12-11

申请号：US13910619

申请日：2013-06-05

Applicant: International Business Machines Corporation

Inventor： Tze-Chiang Chen ,  Bahman Hekmatshoar-Tabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/808 ,  H01L29/737 ,  H01L29/04

CPC classification number: H01L27/0623 ,  G11C11/00 ,  G11C11/412 ,  H01L21/8249 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/205 ,  H01L29/22 ,  H01L29/225 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66901 ,  H01L29/66916 ,  H01L29/66924 ,  H01L29/735 ,  H01L29/737 ,  H01L29/808

Abstract: Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level.

公开(公告)号：US08885395B2

公开(公告)日：2014-11-11

申请号：US13402123

申请日：2012-02-22

Applicant: Yuchen Zhou ,  Zihui Wang ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Roger K. Malmhall

Inventor： Yuchen Zhou ,  Zihui Wang ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Roger K. Malmhall

IPC: G11C11/00

CPC classification number: G11C11/00 ,  G11C11/161 ,  G11C11/1673 ,  H01L27/222 ,  H01L43/08

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.

Abstract translation: 描述了包含共享共同自由层（CFL）的两个串联MTJ的磁阻逻辑单元（MRLC）。 MTJ-1中CFL和可切换参考层（SRL）的相对磁化取向主导了MRLC的总体电阻，而不考虑MTJ-2中不可切换参考层的固定磁化方向。 当可切换参考和公共自由层具有相反的磁化方向时，MRLC的高电阻状态发生。 当取向相同时，发生低电阻状态。 此行为允许将MRLC用作逻辑比较器。 通过施加不切换SRL的选定的相对较短的电压脉冲，通过STT效应来切换CFL。 通过由不会切换CFL的选定的较长电压脉冲产生的电压效应，SRL将根据CFL进行切换。

公开(公告)号：US08879313B2

公开(公告)日：2014-11-04

申请号：US14297243

申请日：2014-06-05

Applicant: SK Hynix Inc.

Inventor： Hae Chan Park ,  Soo Gil Kim

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/00 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/0092 ,  Y10S977/754

Abstract: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

Abstract translation: 一种半导体集成电路系统包括：相变线，包括构成第一存储单元的第一相变区和构成第二存储单元的第二相变区;写入电流提供单元，被配置为对 第一相变区和第二相变区，以及相变补偿单元，被配置为通过补偿由于相位而在另一个相变区域中引起的虚拟相位变化来恢复第一和第二相变区域中的另一个 - 所选择的相变区域的更换。

公开(公告)号：US20140293689A1

公开(公告)日：2014-10-02

申请号：US14301458

申请日：2014-06-11

Applicant: SK hynix Inc.

Inventor： Taek Sang SONG ,  Dae Han KWON

IPC: G11C13/00

CPC classification number: G11C11/00 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract translation: 半导体存储装置包括电阻式存储单元; 数据感测单元，被配置为基于参考电压感测由提供给所述电阻性存储单元的感测电流形成的输出电压，以及输出具有与所述感测结果对应的值的数据; 以及参考电压产生单元，包括分别包括具有第一和第二电阻值的第一和第二电阻器的虚拟存储单元，并且被配置为输出由提供给虚拟存储单元的感测电流形成的电压作为参考电压。

公开(公告)号：US20140286089A1

公开(公告)日：2014-09-25

申请号：US14297213

申请日：2014-06-05

Applicant: SK HYNIX INC.

Inventor： Hae Chan PARK ,  Soo Gil KIM

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/00 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/0092 ,  Y10S977/754

Abstract: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

Abstract translation: 一种半导体集成电路系统包括：相变线，包括构成第一存储单元的第一相变区和构成第二存储单元的第二相变区;写入电流提供单元，被配置为对 第一相变区和第二相变区，以及相变补偿单元，被配置为通过补偿由于相位而在另一个相变区域中引起的虚拟相位变化来恢复第一和第二相变区域中的另一个 - 所选择的相变区域的更换。

公开(公告)号：US08837209B2

公开(公告)日：2014-09-16

申请号：US13582955

申请日：2011-02-17

Applicant: Hideo Ohno ,  Shoji Ikeda ,  Katsuya Miura ,  Kazuo Ono ,  Riichiro Takemura ,  Hiromasa Takahashi

Inventor： Hideo Ohno ,  Shoji Ikeda ,  Katsuya Miura ,  Kazuo Ono ,  Riichiro Takemura ,  Hiromasa Takahashi

IPC: G11C11/00 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  Y10S977/935

Abstract: A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element 101 of the magnetic memory cell, a mechanism 601-604 for dropping the threshold magnetization switching current on “1” writing is provided that applies a magnetic field that is in the inverse direction of the pinned layer to the recording layer of the magnetoresistance effect element.

Abstract translation: 优选磁存储器的选择晶体管的驱动电流与磁阻效应元件的阈值磁化开关电流之间的关系。 为了优化选择晶体管的驱动电流与磁存储单元的磁阻效应元件101的阈值磁化开关电流之间的关系，用于将阈值磁化开关电流降低到“1”写入的机构601-604是 只要将与钉扎层反方向的磁场施加到磁阻效应元件的记录层即可。

公开(公告)号：US20140237200A1

公开(公告)日：2014-08-21

申请号：US13771370

申请日：2013-02-20

Applicant: APPLE INC.

Inventor： Ronen Dar

IPC: G06F11/14

CPC classification number: G11C16/3427 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0246 ,  G11C11/00 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422 ,  G11C16/3431 ,  G11C29/52

Abstract: A method includes storing data in a memory that includes multiple analog memory cells. After storing the data, an interference caused by a first group of the analog memory cells to a second group of the analog memory cells is estimated. The data stored in the first group is reconstructed based on the estimated interference caused by the first group to the second group.

Abstract translation: 一种方法包括将数据存储在包括多个模拟存储器单元的存储器中。 在存储数据之后，估计由第一组模拟存储单元引起的对第二组模拟存储单元的干扰。 基于由第一组到第二组引起的估计干扰来重构存储在第一组中的数据。