Semiconductor device with fin and related methods

    公开(公告)号:US10177255B2

    公开(公告)日:2019-01-08

    申请号:US15723152

    申请日:2017-10-02

    摘要: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

    Semiconductor device with fins including sidewall recesses

    公开(公告)号:US10153371B2

    公开(公告)日:2018-12-11

    申请号:US14175215

    申请日:2014-02-07

    IPC分类号: H01L29/78 H01L29/66

    摘要: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

    Leadframe package with side solder ball contact and method of manufacturing

    公开(公告)号:US10141246B2

    公开(公告)日:2018-11-27

    申请号:US15952068

    申请日:2018-04-12

    摘要: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

    DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance

    公开(公告)号:US10128327B2

    公开(公告)日:2018-11-13

    申请号:US14266384

    申请日:2014-04-30

    发明人: John H. Zhang

    摘要: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.