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公开(公告)号:US10199505B2
公开(公告)日:2019-02-05
申请号:US15620444
申请日:2017-06-12
发明人: John H. Zhang
IPC分类号: H01L29/786 , H01L29/775 , H01L29/66 , H01L29/40 , H01L29/417 , H01L29/778 , H01L29/41 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/165
摘要: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
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公开(公告)号:US10177255B2
公开(公告)日:2019-01-08
申请号:US15723152
申请日:2017-10-02
发明人: Pierre Morin , Nicolas Loubet
IPC分类号: H01L29/00 , H01L29/78 , H01L29/66 , H01L29/165 , H01L27/088
摘要: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
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73.
公开(公告)号:US10170475B2
公开(公告)日:2019-01-01
申请号:US15448626
申请日:2017-03-03
发明人: Stephane Allegret-Maret , Kangguo Cheng , Bruce Doris , Prasanna Khare , Qing Liu , Nicolas Loubet
IPC分类号: H01L29/66 , H01L27/092 , H01L27/11 , H01L21/8238 , H01L21/84 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/762 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/417
摘要: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.
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公开(公告)号:US10153371B2
公开(公告)日:2018-12-11
申请号:US14175215
申请日:2014-02-07
发明人: Xiuyu Cai , Qing Liu , Ruilong Xie
摘要: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.
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公开(公告)号:US10141246B2
公开(公告)日:2018-11-27
申请号:US15952068
申请日:2018-04-12
发明人: Jefferson Talledo , Tito Mangaoang
摘要: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
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公开(公告)号:US10134898B2
公开(公告)日:2018-11-20
申请号:US14982052
申请日:2015-12-29
发明人: Jocelyne Gimbert
IPC分类号: H01L29/78 , H01L21/265 , H01L21/324 , H01L21/70 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/16 , H01L29/161 , H01L29/66 , H01L29/165
摘要: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
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77.
公开(公告)号:US10134759B2
公开(公告)日:2018-11-20
申请号:US14182601
申请日:2014-02-18
发明人: Nicolas Loubet , James Kuss
IPC分类号: H01L21/8238 , H01L27/12 , H01L27/092 , H01L21/84 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/786 , H01L21/02
摘要: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.
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78.
公开(公告)号:US10128327B2
公开(公告)日:2018-11-13
申请号:US14266384
申请日:2014-04-30
发明人: John H. Zhang
IPC分类号: H01L49/02 , H01L27/108 , H01L27/115 , H01L21/28 , H01L21/02 , H01L27/11507
摘要: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.
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公开(公告)号:US10123491B2
公开(公告)日:2018-11-13
申请号:US14985128
申请日:2015-12-30
发明人: Marco De Fazio , Simon Dodd
摘要: The present disclosure is directed to a greenhouse or single container for plant growth coupled to the Internet of Things and including a microfluidic die for water or nutrient distribution. The microfluidic die is controllable automatically or with instructions from a remote user, based on sensors included within a growth environment.
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公开(公告)号:US10117068B2
公开(公告)日:2018-10-30
申请号:US14849823
申请日:2015-09-10
发明人: Oleg Logvinov , Aidan Cully , David Lawrence , Michael Macaluso
IPC分类号: H04W4/06 , H04W74/08 , H04L29/06 , H04L12/413 , H04L1/18 , H04L12/18 , H04B3/54 , H04L12/761 , H04L1/00
摘要: Multicast transmissions do not allow for individual receivers to acknowledge that data was received by each receiver in the network. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol supports using multicast transmissions (one-to-many) in multimedia isochronous systems. A transmitter establishes a Multi-ACKed Multicast protocol within which a group of receiving devices can acknowledge the multicast transmission during a multi-acknowledgment period.
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