公开(公告)号：US06047288A

公开(公告)日：2000-04-04

申请号：US683950

申请日：1996-07-19

Applicant: Takahiro Kurosawa ,  Hiroaki Sato

Inventor： Takahiro Kurosawa ,  Hiroaki Sato

IPC: G06Q10/00 ,  G06F12/14

CPC classification number: G06Q10/10 ,  Y10S707/99938 ,  Y10S707/99939

Abstract: The present invention relates to a group environment setting method in a system where plural participants form a group and perform a cooperative operation. Environment setting information for an application environment setting of a cooperative operation is registered in a group unit. When a group is designated by a participant, environment setting information corresponding to the designated group is read from the registered environment setting information, and applied as environment setting information of the participant. A data structure of the environment setting information has a hierarchical structure, and information related to the designated environment setting items is selected from the read environment setting information.

Abstract translation: 本发明涉及一种系统中的组环境设置方法，其中多个参与者形成一组并进行协作操作。 用于协作操作的应用环境设置的环境设置信息被登记在组单元中。 当由参与者指定组时，从注册环境设置信息读取与指定组对应的环境设置信息，并作为参与者的环境设置信息应用。 环境设置信息的数据结构具有层次结构，并且从读取环境设置信息中选择与指定环境设置项目相关的信息。

公开(公告)号：US5570115A

公开(公告)日：1996-10-29

申请号：US450099

申请日：1995-05-25

Applicant: Tomoaki Kawai ,  Hiroaki Sato

Inventor： Tomoaki Kawai ,  Hiroaki Sato

IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06

CPC classification number: G09G5/06

Abstract: An image processor having a display unit capable of displaying a plurality of color images. The display unit is provided with an administrating section for collectively managing color maps, thereby enabling a color map to be efficiently used in common for display of a plurality of images.

Abstract translation: 一种具有能够显示多个彩色图像的显示单元的图像处理器。 显示单元设置有用于共同管理彩色图的管理部分，从而能够有效地使用彩色图来显示多个图像。

公开(公告)号：US5233239A

公开(公告)日：1993-08-03

申请号：US880835

申请日：1992-05-11

Applicant: Hiroaki Sato

Inventor： Hiroaki Sato

IPC: H03K19/013 ,  H03K19/086

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: An ECL output circuit comprises a current switching circuit of the differential circuit type including a first transistor having a base connected to receive an input voltage and a second transistor having a base connected to a first reference voltage. A third transistor of an emitter follower has a base connected to a collector of the second transistor and an emitter connected to an output terminal. There is also provided an output level detection and feedback circuit including a differential circuit composed of fourth and fifth transistors having their emitters connected in common to a constant current. The fourth transistor has a base connected to the output terminal and a collector connected to the common-connected emitters of the first and second transistors. The fifth transistor has a base connected to a second reference voltage which determines a low level voltage of an output voltage. A sixth transistor is connected in parallel to the fifth transistor and has a base connected to receive the input voltage. Thus, it becomes unnecessary to lower the low level voltage of the output voltage, and the operating margin is not reduced. In addition, a high switching speed can be obtained.

Abstract translation: ECL输出电路包括差分电路类型的电流切换电路，包括具有连接以接收输入电压的基极的第一晶体管和具有连接到第一参考电压的基极的第二晶体管。 射极跟随器的第三晶体管具有连接到第二晶体管的集电极的基极和连接到输出端子的发射极。 还提供了一种输出电平检测和反馈电路，其包括由第四和第五晶体管组成的差分电路，其中发射极共同连接到恒定电流。 第四晶体管具有连接到输出端子的基极和连接到第一和第二晶体管的共同连接的发射极的集电极。 第五晶体管具有连接到第二参考电压的基极，其确定输出电压的低电平电压。 第六晶体管并联连接到第五晶体管，并具有连接以接收输入电压的基极。 因此，不需要降低输出电压的低电平电压，并且不降低运行裕度。 此外，可以获得高切换速度。

公开(公告)号：US5182074A

公开(公告)日：1993-01-26

申请号：US734131

申请日：1991-07-22

Applicant: Osami Yoshioka ,  Naoki Matsui ,  Hiroaki Sato ,  Kouji Omori ,  Masayuki Yamazaki ,  Masafumi Suzuki ,  Hitoshi Oishi ,  Naoto Kitagawa ,  Takaya Seike ,  Yasuhiro Araki

Inventor： Osami Yoshioka ,  Naoki Matsui ,  Hiroaki Sato ,  Kouji Omori ,  Masayuki Yamazaki ,  Masafumi Suzuki ,  Hitoshi Oishi ,  Naoto Kitagawa ,  Takaya Seike ,  Yasuhiro Araki

IPC: C21D1/613 ,  C21D9/573

CPC classification number: C21D9/573 ,  C21D1/613 ,  C21D9/5737

Abstract: An apparatus for continuously cooling a metal strip, which comprises: at least one cooling roll, which is freely rotatable and in contact with a metal strip continuously travelling in the longitudinal direction thereof, for continuously cooling the metal strip, a cooling liquid flowing through the interior of the cooling roll to continuously cool same, a contact area between the surface of the cooling roll and the surface of the metal strip being controllable; and a gas cooler, arranged on the exist side of the at least one cooling roll, for continuously cooling the metal strip by blowing a cooling gas onto the surface of the metal strip so as to achieve a uniform temperature distribution in the width direction of the metal strip after the final cooling thereof, the gas cooler comprising a plurality of mutually independent nozzle headers for blowing the cooling gas onto the surface of the metal strip, and the plurality of nozzle headers controlling at least one of a flow rate and a flow velocity of the cooling gas in the width direction of the metal strip.

Abstract translation: 一种用于连续冷却金属带的装置，包括：至少一个冷却辊，其可自由旋转并与沿其纵向方向连续行进的金属条接触，用于连续冷却所述金属带，流过所述金属带的冷却液 冷却辊的内部连续冷却，冷却辊的表面与金属带的表面之间的接触区域是可控的; 以及设置在所述至少一个冷却辊的存在侧的气体冷却器，用于通过向所述金属带的表面吹入冷却气体来连续地冷却所述金属带，以便在所述金属带的宽度方向上实现均匀的温度分布 金属条在其最终冷却之后，所述气体冷却器包括多个相互独立的喷嘴头，用于将所述冷却气体吹送到所述金属带的表面上，并且所述多个喷嘴头控制流量和流速中的至少一个 的冷却气体在金属带的宽度方向上。

公开(公告)号：US4885681A

公开(公告)日：1989-12-05

申请号：US691909

申请日：1985-01-16

Applicant: Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

Inventor： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

IPC: G06F9/455 ,  G06F9/46 ,  G06F12/08 ,  G06F12/10 ,  G06F13/10

CPC classification number: G06F13/10 ,  G06F9/45558 ,  G06F2009/45579

Abstract: In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "0", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption control mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

Abstract translation: 在能够在一个实际计算机系统下同时运行至少一个操作系统（OS）的虚拟机系统（VMS）和用于控制VMS的控制程序（VMCP）的情况下，目的是减少模拟VM I / Os通过直接I / O执行。 实际子信道控制块的VM信息区域具有包含表示子信道为专用的标志的状态字段。 当标志为“0”时，这意味着该子信道专用于该VM，并且该VMCP的子信道调度是不必要的。 由于真正的中断优先级顺序专用于VM，因此只有VM的I / O中断请求被排队到该专用优先级顺序的实际中断请求队列中，并且避免了该实际中断优先级顺序的VM的混合。 当VM上的OS的中断优先级顺序的中断控制掩码为“0”，表示VM不能接受中断时，相应的专用实际中断优先级顺序的中断控制掩码也为“0”，并且 硬件中断不会发生。 因此，中断由硬件保留，并且避免VMCP对VM的I / O中断保持。

公开(公告)号：US4642508A

公开(公告)日：1987-02-10

申请号：US709600

申请日：1985-03-08

Applicant: Hitoshi Suzuki ,  Hiroaki Sato

Inventor： Hitoshi Suzuki ,  Hiroaki Sato

IPC: H03H3/02 ,  H03H3/04 ,  H03H9/02 ,  H03H9/17 ,  H03H9/56 ,  H01L41/08

CPC classification number: H03H9/173 ,  H01L41/316 ,  H01L41/331 ,  H01L41/332 ,  H03H3/04 ,  H03H9/02102 ,  H03H9/02133 ,  H03H9/564

Abstract: The present invention provides a piezoelectric thin-film resonator comprising a non-piezoelectric film layer formed on a substrate, a lower electrode, a piezoelectric film layer and an upper electrode. An air-gap layer is formed between the non-piezoelectric film and the substrate to facilitate vibration of the piezoelectric film layer at the resonate frequency. The resulting resonating device is mechanically strong while at the same time being capable of operating at high frequency.

Abstract translation: 本发明提供一种压电薄膜谐振器，其包括在基板，下电极，压电薄膜层和上电极上形成的非压电薄膜层。 在非压电膜和基板之间形成气隙层，以便于谐振频率下的压电膜层的振动。 所产生的谐振装置机械强度高，同时能够在高频下工作。

公开(公告)号：US4512012A

公开(公告)日：1985-04-16

申请号：US465604

申请日：1983-02-10

Applicant: Takeshi Sampei ,  Norio Miyahara ,  Tadanobu Nikaido ,  Hiroaki Sato ,  Keizo Aoyama

Inventor： Takeshi Sampei ,  Norio Miyahara ,  Tadanobu Nikaido ,  Hiroaki Sato ,  Keizo Aoyama

IPC: H04Q3/52 ,  H04Q11/04 ,  H04Q11/06 ,  H04J3/00

CPC classification number: H04Q11/06

Abstract: A time-switch circuit for use in a primary time switch (PTSW), a secondary time switch (STSW), and a space switch (SSW) of a digital time-division switching system is disclosed. The time switch comprises a plurality of memory circuits (MUC.sub.11 to MUC.sub.15, MUC.sub.21 to MUC.sub.25). Each memory circuit comprises a memory unit (MEM), an address buffer (AB) for a first address, an m-ary counter (T-CTR) for a second address, an address selector (AS) for selecting either the first or second address, an input data buffer (IB), and an output data buffer (OB). In a write cycle, input data from the input data buffer is written into the memory unit by either the first or second address signal, and in a read cycle, output data is read out of the memory unit by either the second or first address. Selection of the first and second addresses is performed by the address selector, which is controlled by an address-selection mode switch circuit (M.sub.0). Further, the write enable mode of the memory unit is controlled by a write mode switch circuit (M.sub.1).

Abstract translation: 公开了一种用于数字时分交换系统的主时间切换（PTSW），二次时间切换（STSW）和空间切换（SSW）的时间切换电路。 时间开关包括多个存储电路（MUC11至MUC15，MUC21至MUC25）。 每个存储器电路包括存储器单元（MEM），用于第一地址的地址缓冲器（AB），用于第二地址的微计数器（T-CTR），用于选择第一或第二地址的地址选择器 地址，输入数据缓冲器（IB）和输出数据缓冲器（OB）。 在写周期中，通过第一或第二地址信号将来自输入数据缓冲器的输入数据写入存储器单元，并且在读周期中，通过第二或第一地址从存储器单元读出输出数据。 第一和第二地址的选择由地址选择器执行，由地址选择模式切换电路（M0）控制。 此外，存储器单元的写使能模式由写模式开关电路（M1）控制。

公开(公告)号：US09137903B2

公开(公告)日：2015-09-15

申请号：US13157722

申请日：2011-06-10

Applicant: Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

Inventor： Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC: H05K1/11 ,  H05K3/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/81 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8138 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/831 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0195 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Abstract translation: 微电子组件可以包括包括具有导电元件的刚性介电层的基板，具有在其表面暴露的多个触点的微电子元件以及延伸穿过刚性介电层上的柔性介电层的导电通孔。 通孔将基板触点分别电连接到导电元件，并且基板触点分别连接到微电子元件的触点。 通孔，柔性层和衬底触点适于明显地减轻与组件的差分热接触和膨胀相关联的衬底触点处的应力。

公开(公告)号：US08785790B2

公开(公告)日：2014-07-22

申请号：US13293698

申请日：2011-11-10

Applicant: Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Hiroaki Sato ,  Philip Damberg

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Hiroaki Sato ,  Philip Damberg

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract translation: 组件包括具有第一和第二间隔开并平行表面的支撑结构以及沿第一和第二表面之间的方向延伸的多个导电元件。 每个导电元件包含选自铜，铝，镍和铬的布线金属的合金和选自由镓，锗，铟，硒，锡，硫，银，磷和 铋。 该合金具有随导电元件的至少一个方向上的距离而变化的组成。 添加剂的浓度小于或等于导电元件的总原子质量的5％，并且导电元件的电阻率在2.5至30微欧姆厘米之间。

公开(公告)号：US08558169B2

公开(公告)日：2013-10-15

申请号：US13388970

申请日：2010-07-29

Applicant: Masaru Hori ,  Hiroaki Sato ,  Yasutake Toyoshima ,  Mineo Hiramatsu

Inventor： Masaru Hori ,  Hiroaki Sato ,  Yasutake Toyoshima ,  Mineo Hiramatsu

IPC: H01J49/00

CPC classification number: G01N27/622

Abstract: An object of the present invention is to provide a sample substrate for laser desorption ionization mass spectrometry for LDI-MS which substrate enables mass spectrometric analysis of a sample correctly at high sensitivity without generating interference peaks upon irradiation of the sample to laser light and uniform application of the sample onto a base. Another object of the invention is to provide a mass spectrometer (device) employing the sample substrate.In the sample substrate for laser desorption ionization mass spectrometry, the sample substrate is formed of a base and carbon nanowalls having wall surfaces onto which a sample to undergo mass spectrometry is applied, wherein the carbon nanowalls are formed on the base so as to stand on the base. The surfaces of carbon nanowalls serve as an ionization medium and hydrophilized. By use of the sample substrate, mass spectrometry of a sample having a wide range (high to low) molecular weight can be reliably performed at high precision and sensitivity.

Abstract translation: 本发明的目的是提供一种用于LDI-MS的激光解吸电离质谱的样品基片，该基片能够以高灵敏度正确地对样品进行质谱分析，而不会在将样品照射到激光上并产生均匀的应用时产生干涉峰 的样品到基底上。 本发明的另一个目的是提供一种采用样品基质的质谱仪（装置）。 在用于激光解吸电离质谱的样品衬底中，样品衬底由具有壁表面的基底和碳纳米壁形成，其上应用要进行质谱的样品，其中碳纳米壁形成在基底上以便立在 的基地。 碳纳米壁的表面用作电离介质并亲水化。 通过使用样品基板，可以以高精度和灵敏度可靠地进行具有宽范围（高低分子量）的样品的质谱分析。