公开(公告)号：US20240379653A1

公开(公告)日：2024-11-14

申请号：US18782939

申请日：2024-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US11749739B2

公开(公告)日：2023-09-05

申请号：US17396385

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L29/516 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78696

Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

公开(公告)号：US11586901B2

公开(公告)日：2023-02-21

申请号：US17094356

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US11189600B2

公开(公告)日：2021-11-30

申请号：US16861029

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L25/065 ,  H01L23/532 ,  H01L23/00

Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

公开(公告)号：US11088258B2

公开(公告)日：2021-08-10

申请号：US16802381

申请日：2020-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28 ,  H01L27/092

Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

公开(公告)号：US11081590B2

公开(公告)日：2021-08-03

申请号：US16591458

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd. ,  Board of Regents, The University of Texas System

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US10860923B2

公开(公告)日：2020-12-08

申请号：US15488419

申请日：2017-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US10854591B2

公开(公告)日：2020-12-01

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US10700068B2

公开(公告)日：2020-06-30

申请号：US16227701

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L21/84 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.

公开(公告)号：US10566330B2

公开(公告)日：2020-02-18

申请号：US15977949

申请日：2018-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.