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    Magnetic field sensing using magnetoresistive random access memory (MRAM) cells
    71.
    发明授权
    Magnetic field sensing using magnetoresistive random access memory (MRAM) cells 有权
    使用磁阻随机存取存储器（MRAM）单元的磁场感测

    公开(公告)号：US08848431B2

    公开(公告)日：2014-09-30

    申请号：US13561478

    申请日：2012-07-30

    Applicant: Romney R. Katti ,  Michael A. Smith

    Inventor： Romney R. Katti ,  Michael A. Smith

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C29/04

    Abstract: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell.

    Abstract translation: 磁场感测系统包括一个或多个磁阻随机存取存储器（MRAM）单元，并且可以被配置为确定入射到MRAM单元上的外部磁场的存在，大小和极性中的一个或多个。 在一些示例中，系统的控制模块控制写入电流源或另一个器件，以通过与MRAM单元相关联的写入线提供写入电流，以引导靠近MRAM单元的磁场。 磁场可能小于MRAM单元的磁切换阈值。 在开始通过写入线提供写入电流之后，控制模块可以确定MRAM单元的磁状态，并且至少部分地基于MRAM单元的磁状态来确定入射到MRAM单元上的外部磁场的存在 MRAM单元。

    Spintronic devices with integrated transistors
    74.
    发明授权
    Spintronic devices with integrated transistors 有权
    带集成晶体管的Spintronic器件

    公开(公告)号：US08503224B2

    公开(公告)日：2013-08-06

    申请号：US13448076

    申请日：2012-04-16

    Applicant: Romney R. Katti ,  Theodore Zhu

    Inventor： Romney R. Katti ,  Theodore Zhu

    IPC: G11C11/00

    CPC classification number: G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

    Abstract translation: 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

    CONFIGURABLE REFERENCE CIRCUIT FOR LOGIC GATES
    75.
    发明申请
    CONFIGURABLE REFERENCE CIRCUIT FOR LOGIC GATES 有权
    逻辑门配置参考电路

    公开(公告)号：US20120319727A1

    公开(公告)日：2012-12-20

    申请号：US13161070

    申请日：2011-06-15

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: H03K19/16

    CPC classification number: H03K19/16

    Abstract: This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the reference current the magnetic logic device may be caused to implement different combinational logic functions.

    Abstract translation: 本公开涉及用于基于将由磁逻辑器件执行的组合逻辑功能来产生参考电流的技术。 比较器电路可以比较流过磁逻辑器件的读取电流的幅度和参考电流，以便当将组合逻辑功能应用于输入值时产生对应于逻辑输出值的逻辑输出值。 通过为参考电流选择适当的幅度，可以使磁逻辑器件实现不同的组合逻辑功能。

    SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS
    76.
    发明申请
    SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS 有权
    具有集成晶体管的旋转器件

    公开(公告)号：US20110280063A1

    公开(公告)日：2011-11-17

    申请号：US13193523

    申请日：2011-07-28

    Applicant: Romney R. Katti ,  Theodore Zhu

    Inventor： Romney R. Katti ,  Theodore Zhu

    IPC: G11C11/16

    CPC classification number: G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

    Abstract translation: 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

    Partitioned random access and read only memory
    77.
    发明授权
    Partitioned random access and read only memory 有权
    分区随机访问和只读内存

    公开(公告)号：US07746686B2

    公开(公告)日：2010-06-29

    申请号：US11409371

    申请日：2006-04-21

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00 ,  G11C8/00

    CPC classification number: G11C11/005 ,  G11C7/24 ,  G11C11/1673 ,  G11C11/1675

    Abstract: A magnetic memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive bit. The memory cells may each be coupled to a current driver. Each current driver may be inhibited so that it does not output a current. Inhibiting the output current prevents the memory from being written. By inhibiting some current drivers and not inhibiting other current drivers, the memory may be partitioned into read only and random access portions.

    Abstract translation: 描述了磁存储器和操作存储器的方法。 存储器包括可以各自包括磁阻位的存储器单元。 每个存储器单元可以耦合到当前驱动器。 可以禁止每个电流驱动器，使其不输出电流。 禁止输出电流防止写入内存。 通过抑制一些当前驱动器并且不阻止其他当前驱动器，存储器可以被划分为只读和随机访问部分。

    State save-on-power-down using GMR non-volatile elements
    79.
    发明授权
    State save-on-power-down using GMR non-volatile elements 有权
    使用GMR非易失性元素的状态保存掉电

    公开(公告)号：US07372723B1

    公开(公告)日：2008-05-13

    申请号：US11464049

    申请日：2006-08-11

    Applicant: Yong Lu ,  Romney R. Katti

    Inventor： Yong Lu ,  Romney R. Katti

    IPC: G11C11/00

    CPC classification number: G11C11/005 ,  G11C14/0036 ,  G11C14/0081

    Abstract: The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated giant-magneto-resistive (GMR) structures. In an embodiment, a save-on-power-down circuit that may be integrated with conventional semiconductor-based computing, logic, and memory devices to retain volatile logic states and/or volatile digital information in a non-volatile manner is provided.

    Abstract translation: 半导体行业旨在通过改进的非易失性存储设备降低传统易失性存储设备的风险。 对于显着提升，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 在一个实施例中，提供了可以与常规的基于半导体的计算，逻辑和存储器装置集成以保持易失性逻辑状态和/或非易失性方式的易失性数字信息的保存在掉电电路。

    Separate write and read access architecture for a magnetic tunnel junction
    80.
    发明授权
    Separate write and read access architecture for a magnetic tunnel junction 有权
    用于磁性隧道结的独立的写入和读取访问架构

    公开(公告)号：US07366009B2

    公开(公告)日：2008-04-29

    申请号：US10754880

    申请日：2004-01-10

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00

    CPC classification number: G11C11/15 ,  H01L27/222

    Abstract: A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line is coupled to a first ferromagnetic layer and a second read line is coupled to a second ferromagnetic layer such that a voltage difference between the two read lines will produce a current flowing perpendicularly through each layer of the MTJ. A first write line is separated from the first read line by a first insulator and a second write line is separated from the second read line by a second insulator.

    Abstract translation: 磁阻器件具有单独的读和写结构。 在一个实施例中，磁性隧道结（MTJ）具有夹在两个铁磁性导电层之间的非磁性非导电阻挡层。 第一读取线耦合到第一铁磁层，并且第二读取线耦合到第二铁磁层，使得两个读取线之间的电压差将产生垂直于MTJ的每个层流动的电流。 第一写入线通过第一绝缘体与第一读取线分离，并且第二写入线通过第二绝缘体与第二读取线分离。

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