公开(公告)号：US06683346B2

公开(公告)日：2004-01-27

申请号：US10092692

申请日：2002-03-07

Applicant: Jun Zeng

Inventor： Jun Zeng

IPC: H01L2976

CPC classification number: H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract translation: 功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。 在衬底上有相同掺杂的更轻掺杂的外延层。 外延层上方是由相反型掺杂形成的阱区。 覆盖阱是重掺杂的第一导电类型的上源层。 沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。 沟槽的底部填充有掺杂多晶硅屏蔽层。 诸如氮化硅的层间电介质覆盖屏蔽。 栅极区域由另一层掺杂多晶硅形成。 第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。 在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

公开(公告)号：US06445035B1

公开(公告)日：2002-09-03

申请号：US09624533

申请日：2000-07-24

Applicant: Jun Zeng ,  Gary M. Dolny ,  Christopher B. Kocon ,  Linda S. Brush

Inventor： Jun Zeng ,  Gary M. Dolny ,  Christopher B. Kocon ,  Linda S. Brush

IPC: H01L2994

CPC classification number: H01L29/7802 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7813

Abstract: An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.

Abstract translation: MOS功率器件的衬底包括具有上表面和下面的漏极区的上层，设置在漏极区上的上层中的第一导电类型的阱区，以及多个间隔开的掩埋栅， 包括从上层的上表面穿过阱区延伸到漏区的沟槽。 每个沟槽包括衬在其表面上的绝缘材料，将其下部填充到基本上在上层的上表面下方的选定水平的导电材料，以及基本上填充沟槽其余部分的绝缘材料。 第二导电类型的多个高掺杂源区被设置在邻近每个沟槽的上部的上层中，每个源区从上表面延伸到上层中的深度，以提供源区和 沟槽中的导电材料。 每个高掺杂源区域中的沟槽延伸穿过源区域进入阱区域并终止于最低点。 第一导电类型的高掺杂体区域设置在与一个或多个凹槽的最低点相邻的阱区域中以及与沟槽穿透的相邻源极区域相邻的阱区域中。 导电层设置在衬底上并与主体区域和源区域电接触。 制造器件的工艺产生了MOS功率器件，其避免了沟道宽度的损失，并且在不牺牲器件耐用性和动态特性的情况下提供降低的沟道电阻。

公开(公告)号：US06351009B1

公开(公告)日：2002-02-26

申请号：US09260411

申请日：1999-03-01

Applicant: Christopher B. Kocon ,  Jun Zeng

Inventor： Christopher B. Kocon ,  Jun Zeng

IPC: H01L2976

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

Abstract translation: 改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。 上层还在其上表面包括多个重掺杂的源极区域，其具有与主体区域A相反的第二极性。栅极沟槽从上层的上表面延伸到漏极区域，并且将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽用导电栅极材料填充到选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面 的设备。

公开(公告)号：US6104062A

公开(公告)日：2000-08-15

申请号：US107721

申请日：1998-06-30

Applicant: Jun Zeng

Inventor： Jun Zeng

IPC: H01L21/331 ,  H01L23/482 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66333 ,  H01L23/4827 ,  H01L24/32 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/7802 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

Abstract: A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical contact layer. The body preferably comprises a material having an electrical resistivity lower than an electrical resistivity of the semiconductor substrate to thereby lower an effective electrical resistivity of the substrate. The device active region may be an active region of a power control device, such as a MOSFET or IGBT, for example. The body may preferably comprise an electrical conductor such as copper, aluminum, silver, solder, or doped polysilicon. The at least one recess and associated resistivity-lowering body preferably defines a proportion of the semiconductor substrate area adjacent the device active region greater than about 0.4 percent, and may extend into the semiconductor substrate a distance greater than about 25 percent of a thickness of the substrate.

Abstract translation: 一种半导体器件包括形成在半导体衬底的第一表面中的至少一个器件有源区，在半导体衬底的第二表面上的电接触层和位于衬底中的相应凹槽中的至少一个电阻率降低体，以及 连接到电接触层。 本体优选地包括具有低于半导体衬底的电阻率的电阻率的材料，从而降低衬底的有效电阻率。 器件有源区可以是功率控制器件的有源区，例如MOSFET或IGBT。 主体可以优选地包括诸如铜，铝，银，焊料或掺杂多晶硅的电导体。 所述至少一个凹部和相关联的电阻率降低体优选地限定与所述器件有源区相邻的所述半导体衬底区域的比例大于约0.4％，并且可以延伸到所述半导体衬底中的距离大于所述半导体衬底的厚度的约25％ 基质。

公开(公告)号：US10789561B2

公开(公告)日：2020-09-29

申请号：US14354714

申请日：2011-11-21

Applicant: Jun Zeng ,  Hamid Reza Motahari Nezhad

Inventor： Jun Zeng ,  Hamid Reza Motahari Nezhad

IPC: G06Q10/06 ,  G06Q50/16 ,  G06Q50/08

Abstract: In one embodiment, a method of recommending a production plan includes calculating a similarity score between an incoming order and each historical order in a historical order database, providing a list of most similar historical orders and corresponding historical production plans ranked according to highest similarity scores, receiving an election indicating a historical production plan as a selected production plan, and admitting the selected historical production plan to fulfill the incoming order.

公开(公告)号：US09235359B2

公开(公告)日：2016-01-12

申请号：US14347273

申请日：2011-10-31

Applicant: Eric Hoarau ,  Jun Zeng ,  Giordano B. Beretta ,  I-Jong Lin

Inventor： Eric Hoarau ,  Jun Zeng ,  Giordano B. Beretta ,  I-Jong Lin

IPC: G06F15/00 ,  G06F3/12 ,  G06K15/00 ,  G06Q10/06

CPC classification number: G06F3/1203 ,  G06F3/121 ,  G06F3/1229 ,  G06F3/1237 ,  G06F3/1273 ,  G06F3/1275 ,  G06F3/1282 ,  G06Q10/0635

Abstract: A system that generates risk values for a print service provider. The print service provider may calculate probabilities of an event occurring, calculate the effect that the given event will have on the print service provider, and determine various risks associated with calculations. These risks may then be utilized to determine overall operational strategies for the print service provider when compared to threshold risk levels for the print service provider.

Abstract translation: 为打印服务提供商生成风险值的系统。 打印服务提供商可以计算事件发生的概率，计算给定事件对打印服务提供商的影响，并确定与计算相关的各种风险。 然后，与打印服务提供商的阈值风险级别相比，可以利用这些风险来确定打印服务提供商的整体操作策略。

公开(公告)号：US20140285848A1

公开(公告)日：2014-09-25

申请号：US14347273

申请日：2011-10-31

Applicant: Eric Hoarau ,  Jun Zeng ,  Giordano B. Beretta ,  I-Jong Lin

Inventor： Eric Hoarau ,  Jun Zeng ,  Giordano B. Beretta ,  I-Jong Lin

IPC: G06F3/12

CPC classification number: G06F3/1203 ,  G06F3/121 ,  G06F3/1229 ,  G06F3/1237 ,  G06F3/1273 ,  G06F3/1275 ,  G06F3/1282 ,  G06Q10/0635

Abstract: A system that generates risk values for a print service provider. The print service provider may calculate probabilities of an event occurring, calculate the effect that the given event will have on the print service provider, and determine various risks associated with calculations. These risks may then be utilized to determine overall operational strategies for the print service provider when compared to threshold risk levels for the print service provider.

Abstract translation: 为打印服务提供商生成风险值的系统。 打印服务提供商可以计算事件发生的概率，计算给定事件对打印服务提供商的影响，并确定与计算相关的各种风险。 然后，与打印服务提供商的阈值风险级别相比，可以利用这些风险来确定打印服务提供商的整体操作策略。

公开(公告)号：US20130278964A1

公开(公告)日：2013-10-24

申请号：US13452813

申请日：2012-04-20

Applicant: Jun Zeng ,  Eric Hoarau ,  I-Jong Lin

Inventor： Jun Zeng ,  Eric Hoarau ,  I-Jong Lin

IPC: G06K15/02

CPC classification number: G06F3/1207 ,  G06F3/121 ,  G06F3/1273 ,  G06F3/1288

Abstract: A system for print service provider (PSP) operations management includes a provenance analytics engine. The provenance analytics engine accesses fresh meta-data associated with fresh events in a PSP operation performed using a printing system operated by a PSP. The provenance analytics engine further accesses stored meta-data associated with past events related to past PSP operations. Still further, the provenance analytics engine accesses a component behavioral model (CBM) to produce results associated with events in a PSP operation. The provenance analytics engine analyzes the event-related meta-data.

Abstract translation: 打印服务提供商（PSP）操作管理系统包括来源分析引擎。 来源分析引擎使用由PSP操作的打印系统执行的PSP操作中访问与新鲜事件相关的新鲜元数据。 来源分析引擎还访问与过去PSP操作相关的过去事件相关联的存储的元数据。 此外，来源分析引擎访问组件行为模型（CBM）以产生与PSP操作中的事件相关联的结果。 来源分析引擎分析事件相关的元数据。

公开(公告)号：US20130278491A1

公开(公告)日：2013-10-24

申请号：US13995446

申请日：2010-12-20

Applicant: Gary Gibson ,  Jun Zeng

Inventor： Gary Gibson ,  Jun Zeng

IPC: G09G3/34

CPC classification number: G09G3/344 ,  B03C5/028 ,  G02F1/167

Abstract: A traveling wave dielectrophoresis display includes a display cell and a plurality of first particles contained within the display cell, the plurality of first particles having a first color. A plurality of electrodes in proximity to the display cell and generate a traveling wave dielectrophoresis field which distributes the plurality of first particles within the display cell to alter its optical characteristics.

Abstract translation: 行波介电电泳显示器包括显示单元和包含在显示单元内的多个第一颗粒，多个第一颗粒具有第一颜色。 在显示单元附近的多个电极，并产生在显示单元内分布多个第一颗粒以改变其光学特性的行波介电电泳场。

公开(公告)号：US08564057B1

公开(公告)日：2013-10-22

申请号：US12835636

申请日：2010-07-13

Applicant: Mohamed N. Darwish ,  Jun Zeng

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

Abstract translation: 侧向功率器件，其中静电静电电荷放置在与漂移区相邻的电介质材料中。 屏蔽栅极介于栅电极和漏极之间，以减少米勒电荷。 在一些实施例中，栅电极是沟槽栅极，并且在这种情况下，屏蔽电极也优选地垂直延伸。