公开(公告)号：US20230065852A1

公开(公告)日：2023-03-02

申请号：US17464788

申请日：2021-09-02

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Nicolas Loubet

IPC分类号： H01L27/092 ,  H01L21/8238

摘要： A semiconductor structure includes a p-type field-effect transistor region and an n-type field-effect transistor region. The p-type field-effect transistor region includes a strained channel of a composite of silicon germanium and silicon. The n-type field-effect transistor region includes a silicon channel.

公开(公告)号：US11515392B2

公开(公告)日：2022-11-29

申请号：US17362369

申请日：2021-06-29

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  International Business Machines Corporation

发明人： Shay Reboh ,  Remi Coquand ,  Nicolas Loubet ,  Tenko Yamashita ,  Jingyun Zhang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/76 ,  H01L29/775

摘要： An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

公开(公告)号：US11450755B2

公开(公告)日：2022-09-20

申请号：US16904138

申请日：2020-06-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

摘要： An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.

公开(公告)号：US11322408B2

公开(公告)日：2022-05-03

申请号：US17130214

申请日：2020-12-22

申请人： International Business Machines Corporation

发明人： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

摘要： A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

公开(公告)号：US11164958B2

公开(公告)日：2021-11-02

申请号：US16752900

申请日：2020-01-27

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Nicolas Loubet ,  Zhenxing Bi ,  Richard A. Conti

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/786

摘要： Provided are embodiments of a method for forming a semiconductor device. The method includes forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises channel layers and nanosheet layers, forming a sacrificial gate over the nanosheet stack, and forming trenches to expose sidewalls of the nanosheet stack. The method also includes forming source/drain (S/D) regions, where forming the S/D regions including forming first portions of the S/D regions on portions of the nano sheet stack, forming second portions of the S/D regions, wherein the first portions are different than the second portions, and replacing the sacrificial gate with a conductive gate material. Also provided are embodiments of a semiconductor device formed by the method described herein.

公开(公告)号：US20210111077A1

公开(公告)日：2021-04-15

申请号：US17130214

申请日：2020-12-22

申请人： International Business Machines Corporation

发明人： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

摘要： A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

公开(公告)号：US10957799B2

公开(公告)日：2021-03-23

申请号：US16286731

申请日：2019-02-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Edward Nowak ,  Yi Qi ,  Kangguo Cheng ,  Nicolas Loubet

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L29/10

摘要： Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：US10910273B2

公开(公告)日：2021-02-02

申请号：US16284682

申请日：2019-02-25

申请人： International Business Machines Corporation

发明人： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

摘要： A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

公开(公告)号：US10832964B1

公开(公告)日：2020-11-10

申请号：US16511647

申请日：2019-07-15

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Chanro Park ,  Nicolas Loubet

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L21/768

摘要： A semiconductor structure is disclosed including a semiconductor substrate having two or more fins. The semiconductor structure includes a recessed gate structure having opposing sidewalls located over one of the fins. The semiconductor structure includes a gate spacer disposed on the opposing sidewalls of the recessed gate structure. The semiconductor structure includes a source/drain region disposed between adjacent gate spacers. The semiconductor structure includes a first conductive material disposed on the source/drain region and an interlevel dielectric layer disposed on a top surface of the semiconductor structure defining an opening therein to an exposed top surface of the first conductive material. A width of an upper portion of the opening is greater than the width of the lower portion of the opening. The lower portion of opening is aligned with the first conductive material. The semiconductor structure includes a second conductive material disposed in the opening.

公开(公告)号：US10818775B2

公开(公告)日：2020-10-27

申请号：US16190747

申请日：2018-11-14

申请人： Commissariat a l'energie atomique et aux energies alternatives ,  International Business Machines Corporation

发明人： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78

摘要： The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.