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公开(公告)号:US10985105B2
公开(公告)日:2021-04-20
申请号:US16168092
申请日:2018-10-23
发明人: John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号: H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00 , H01L23/485 , H01L21/285
摘要: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号:US10964881B2
公开(公告)日:2021-03-30
申请号:US15825171
申请日:2017-11-29
发明人: Bruce G. Elmegreen , Marcelo A. Kuroda , Xiao Hu Liu , Glenn J. Martyna , Dennis M. Newns , Paul M. Solomon
IPC分类号: H01L41/09
摘要: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.
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公开(公告)号:US10928356B2
公开(公告)日:2021-02-23
申请号:US15299762
申请日:2016-10-21
发明人: Paul M. Solomon , Sufi Zafar
IPC分类号: G01N27/414 , G01N27/416 , H01L29/423 , H01L29/10 , H01L29/40
摘要: A substrate's embedded substrate contact electrode forms a reference voltage point. A gate insulator is spaced outwardly from the substrate and has an exposed outer surface configured for contact with a fluid analyte. A device region is intermediate the substrate and the gate insulator; source and drain regions are adjacent the device region; and a field insulator is spaced outwardly of the drain region, the source region, and the substrate away from the device region. The gate insulator and the field oxide are formed of different materials having different chemical sensitivities to the fluid analyte. The field insulator is coupled to the substrate through the field insulator capacitance. The gate insulator capacitance is much smaller than the field insulator capacitance. The embedded substrate contact electrode can be connected to a separate voltage so that the electrical potential between the substrate and the source region can be controlled.
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公开(公告)号:US10777645B2
公开(公告)日:2020-09-15
申请号:US16750157
申请日:2020-01-23
发明人: Guy M. Cohen , Paul M. Solomon , Christian Lavoie
IPC分类号: H01L21/02 , H01L29/36 , H01L29/10 , H01L29/08 , H01L29/732 , H01L29/737 , H01L29/66 , H01L29/207 , H01L23/525 , H01L29/861
摘要: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
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公开(公告)号:US20200161436A1
公开(公告)日:2020-05-21
申请号:US16750157
申请日:2020-01-23
发明人: Guy M. Cohen , Paul M. Solomon , Christian Lavoie
IPC分类号: H01L29/36 , H01L21/02 , H01L29/10 , H01L29/08 , H01L29/732 , H01L29/737 , H01L29/66 , H01L29/207 , H01L23/525 , H01L29/861
摘要: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
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公开(公告)号:US20200035793A1
公开(公告)日:2020-01-30
申请号:US16417985
申请日:2019-05-21
发明人: Guy M. Cohen , Paul M. Solomon , Christian Lavoie
IPC分类号: H01L29/36 , H01L21/02 , H01L29/737 , H01L29/732 , H01L29/08 , H01L29/66 , H01L29/10
摘要: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
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公开(公告)号:US10468432B1
公开(公告)日:2019-11-05
申请号:US15992960
申请日:2018-05-30
IPC分类号: H01L27/1159 , H01L27/11585 , G11C11/56 , H01L27/24 , G11C11/22 , H01L27/11587
摘要: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
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公开(公告)号:US20190312108A1
公开(公告)日:2019-10-10
申请号:US16434711
申请日:2019-06-07
发明人: Yulong Li , Paul M. Solomon , SIYURANGA KOSWATTA
摘要: A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号:US10411101B1
公开(公告)日:2019-09-10
申请号:US16049027
申请日:2018-07-30
发明人: Guy M. Cohen , Paul M. Solomon , Christian Lavoie
IPC分类号: H01L29/66 , H01L29/36 , H01L29/737 , H01L29/732 , H01L29/08 , H01L29/10 , H01L21/02
摘要: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
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公开(公告)号:US10374163B2
公开(公告)日:2019-08-06
申请号:US15803074
申请日:2017-11-03
摘要: A field effect transistor includes a carbon nanotube layer formed adjacent to a gate structure. Two intermetallic contacts are formed on the carbon nanotube layer. The two intermetallic contacts include an oxidation resistant compound having a work function below about 4.4 electron-volts.
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