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公开(公告)号：US10362509B2
公开(公告)日：2019-07-23
申请号：US15656854
申请日：2017-07-21
发明人： Govardhan Mattela
IPC分类号： H04L1/18 , H04W4/02 , H04W28/04 , H04W4/70 , H04W4/90 , H04W4/04 , H04W4/08 , H04W24/08 , H04L1/08 , H04W4/46 , H04L29/12 , H04W84/18 , H04L1/00
摘要： A system for transmission of incident information includes maintaining a table of RSSI values for a plurality of stations. When an incident is detected, the system first sends a broadcast packet with incident information, and next sends a unicast packet to any station below a particular RSSI threshold until the unicast packet is acknowledged or a retransmission interval passes.
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72.发明授权公开(公告)号：US09946323B1
公开(公告)日：2018-04-17
申请号：US15277324
申请日：2016-09-27
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3243 , G06F1/3296 , G06F9/4418 , H04W52/0229 , H04W52/0235 , H04W52/0261 , H04W84/12 , Y02D10/152 , Y02D70/142 , Y02D70/166
摘要： A wake-up processor for a communications processor has a receive signal amplifier for amplifying the signal level of received RF which has been transmitted as wireless local area network WLAN packets, an amplitude detector for indicating the envelope of the RF energy in the packets, a threshold detector which thresholds the detected RF envelope, and a correlator which compares the detected and thresholded RF envelope with a private pseudo-random number to determine the level of correlation between the received value and the private value. When the correlation exceeds a required threshold, a wake-up signal is asserted which is used to bring a WLAN processor into an active state for processing of subsequently sent packets.
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公开(公告)号：US12107966B2
公开(公告)日：2024-10-01
申请号：US17359546
申请日：2021-06-26
发明人： Ananya Shrivastava , Mohammed Sumair , Joydeep Kumar Devnath , Suyash Kandele , Govardhan Mattela
CPC分类号： H04L9/3247 , H04L9/30 , H04L9/3239 , H04L9/3297 , H04L9/50 , H04L2209/805
摘要： An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.
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公开(公告)号：US11893360B2
公开(公告)日：2024-02-06
申请号：US17180856
申请日：2021-02-21
发明人： Dylan Finch
CPC分类号： G06F7/5443 , G06F7/4876 , G06F7/49936 , G06F9/3893
摘要： A process for performing vector dot products receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The process generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits to form a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information including MAX_EXP and EXP_DIFF. A second pipeline stage receives the multiplied pairs of normalized mantissas, optionally performs an exponent adjustment, pads, complements and shifts the normalized mantissas, and the results are added in a series of stages until a single addition result remains, which is normalized using MAX_EXP to form the floating point output result.
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公开(公告)号：US11567730B2
公开(公告)日：2023-01-31
申请号：US17163556
申请日：2021-01-31
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
摘要： A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.
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公开(公告)号：US20220405054A1
公开(公告)日：2022-12-22
申请号：US17352374
申请日：2021-06-21
发明人： Dylan FINCH
摘要： A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.
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公开(公告)号：US11522547B1
公开(公告)日：2022-12-06
申请号：US17334817
申请日：2021-05-31
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
摘要： A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
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公开(公告)号：US20220383002A1
公开(公告)日：2022-12-01
申请号：US17334899
申请日：2021-05-31
发明人： Martin KRAEMER , Ryan BOESCH , Wei XIONG
IPC分类号： G06J1/00
摘要： A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
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79.发明申请公开(公告)号：US20220383001A1
公开(公告)日：2022-12-01
申请号：US17334890
申请日：2021-05-31
发明人： Martin KRAEMER , Ryan BOESCH , Wei XIONG
IPC分类号： G06J1/00
摘要： A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
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公开(公告)号：US20220336729A1
公开(公告)日：2022-10-20
申请号：US17234792
申请日：2021-04-19
摘要： A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.
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