公开(公告)号：US20080130367A1

公开(公告)日：2008-06-05

申请号：US12027735

申请日：2008-02-07

Applicant: Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

Inventor： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

IPC: G11C16/14

CPC classification number: G11C7/18 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11521

Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

Abstract translation: 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

公开(公告)号：US20080089136A1

公开(公告)日：2008-04-17

申请号：US11870762

申请日：2007-10-11

Applicant: Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

Inventor： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

IPC: G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract translation: 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

公开(公告)号：US20080087938A1

公开(公告)日：2008-04-17

申请号：US11905629

申请日：2007-10-03

Applicant: Hee-seog Jeon ,  Jeong-uk Han

Inventor： Hee-seog Jeon ,  Jeong-uk Han

IPC: H01L27/115 ,  H01L27/112 ,  H01L21/8247

CPC classification number: H01L27/11253 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

Abstract: Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed between a source region and a drain region at each of the on-cell and the off-cell. The on-cell may include a cell diffusion region between the select gate pattern and the memory gate pattern.

Abstract translation: 示例性实施例涉及掩模ROM，掩模ROM嵌入式EEPROM及其制造方法。 掩模ROM可以包括选择栅极图案和布置在每个开孔单元和关闭单元之间的源区域和漏极区域之间的存储器栅极图案。 接通单元可以包括选择栅极图案和存储器栅极图案之间的单元扩散区域。

公开(公告)号：US20080054345A1

公开(公告)日：2008-03-06

申请号：US11891605

申请日：2007-08-10

Applicant: Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

Abstract: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

Abstract translation: 提供电可擦除可编程只读存储器（EEPROM）器件和制造EEPROM器件的方法。 在形成在基板上的隧道绝缘层上形成具有相同结构的第一和第二栅极结构，使得第一和第二栅极结构彼此间隔开。 在位于第一和第二栅极结构之间的衬底的一部分处形成公共源区。 第一和第二漏极区分别形成在与第一和第二栅极结构相邻的衬底的第一和第二部分处。 因此，制造EEPROM器件，其包括具有相同结构的第一和第二晶体管，并且可以根据施加的信号交替地用作存储晶体管和选择晶体管。

公开(公告)号：US20080029808A1

公开(公告)日：2008-02-07

申请号：US11837361

申请日：2007-08-10

Applicant: Hee-Seog JEON ,  Seung-Beom YOON ,  Jeong-Uk HAN

Inventor： Hee-Seog JEON ,  Seung-Beom YOON ,  Jeong-Uk HAN

IPC: H01L29/788

CPC classification number: H01L29/7885 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

Abstract translation: 在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。 绝缘浮栅设置在基板上。 浮置栅极至少部分地与第一结区重叠。 在浮动门上设置绝缘的程序门。 程序门具有弯曲的上表面。 半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。 擦除栅极部分地与第二结区重叠。

公开(公告)号：US20080014691A1

公开(公告)日：2008-01-17

申请号：US11774724

申请日：2007-07-09

Applicant: Hee-Seog JEON ,  Jeong-Uk HAN

Inventor： Hee-Seog JEON ,  Jeong-Uk HAN

IPC: H01L21/8234

CPC classification number: H01L27/105 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/11266 ,  H01L27/11293

Abstract: A mask read-only memory (ROM) cell, a method for fabricating the mask ROM cell, a NOR-type mask ROM device, and a method for fabricating the NOR-type mask ROM device are disclosed. A mask ROM cell includes a substrate including an ON cell region and an OFF cell region, a first gate electrode disposed in the ON cell region, and a second gate electrode disposed in the OFF cell region. The mask ROM cell also includes a first impurity region disposed in the substrate proximate a sidewall of the first gate electrode, wherein a portion of the first impurity region is disposed under the first gate electrode; and a second impurity region disposed the substrate proximate a sidewall of the second gate electrode, wherein no portion of the second impurity region is disposed under the second gate electrode.

Abstract translation: 公开了一种掩模只读存储器（ROM）单元，用于制造掩模ROM单元的方法，NOR型掩模ROM器件和用于制造NOR型掩模ROM器件的方法。 掩模ROM单元包括包括ON单元区域和OFF单元区域的基板，设置在ON单元区域中的第一栅极电极和设置在OFF单元区域中的第二栅电极。 掩模ROM单元还包括靠近第一栅电极的侧壁设置在基板中的第一杂质区，其中第一杂质区的一部分设置在第一栅电极下方; 以及第二杂质区域，其将所述基板设置在所述第二栅电极的侧壁附近，其中所述第二杂质区域的部分没有设置在所述第二栅电极下方。

公开(公告)号：US20080012062A1

公开(公告)日：2008-01-17

申请号：US11775871

申请日：2007-07-11

Applicant: Hyun-Khe YOO ,  Jeong-Uk HAN ,  Hee-Seog JEON ,  Sung-Gon CHOI ,  Bo-young SEO ,  Chang-Min JEON ,  Ji-Do RYU

Inventor： Hyun-Khe YOO ,  Jeong-Uk HAN ,  Hee-Seog JEON ,  Sung-Gon CHOI ,  Bo-young SEO ,  Chang-Min JEON ,  Ji-Do RYU

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

Abstract: An electrically erasable programmable read-only memory (EEPROM) device includes an EEPROM cell located on a semiconductor substrate, the EEPROM cell including a memory transistor and a selection transistor. A source region and a drain region are located on the semiconductor substrate adjacent to opposite sides of the EEPROM cell, respectively, and a floating region is positioned between the memory transistor and the selection transistor. The source region includes a first doped region, a second doped region and a third doped region, where the first doped region surrounds a bottom surface and sidewalls of the second doped region, and the second doped surrounds a bottom surface and sidewalls of the third doped region. Also, a second impurity concentration of the second doped region is higher than that of the first doped region and lower than that of the third doped region.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）装置包括位于半导体衬底上的EEPROM单元，EEPROM单元包括存储晶体管和选择晶体管。 源极区域和漏极区域分别位于与EEPROM单元的相对侧相邻的半导体衬底上，并且浮置区域位于存储晶体管和选择晶体管之间。 源极区域包括第一掺杂区域，第二掺杂区域和第三掺杂区域，其中第一掺杂区域围绕第二掺杂区域的底表面和侧壁，第二掺杂区域包围底表面和第三掺杂区域的侧壁 地区。 此外，第二掺杂区域的第二杂质浓度高于第一掺杂区域的第二杂质浓度，并且低于第三掺杂区域的第二杂质浓度。

公开(公告)号：US20080008003A1

公开(公告)日：2008-01-10

申请号：US11789003

申请日：2007-04-23

Applicant: Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

Inventor： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

Abstract: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

Abstract translation: 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，并且第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

公开(公告)号：US20080003810A1

公开(公告)日：2008-01-03

申请号：US11823381

申请日：2007-06-27

Applicant: Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

Inventor： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC: H01L21/4763

CPC classification number: H01L27/1021

Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

Abstract translation: 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US20070262373A1

公开(公告)日：2007-11-15

申请号：US11800650

申请日：2007-05-07

Applicant: Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

Inventor： Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

IPC: H01L29/792

CPC classification number: H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

Abstract: A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region, and a tunneling-prevention dielectric layer pattern. The tunneling dielectric layer is formed on the semiconductor substrate. The memory gate and a select gate are formed on the tunneling dielectric layer to be spaced apart from each other. The floating junction region is formed within the semiconductor substrate between the memory gate and the select gate, the bit line junction region is formed opposite the floating junction region with respect to the memory gate, and a common source region is formed opposite the floating junction region with respect to the select gate. The tunneling-prevention dielectric layer pattern is interposed between the semiconductor substrate and the tunneling dielectric layer, and is configured to overlap part of the memory gate.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，隧道电介质层，存储栅极和选择栅极，浮置结区域，位线结区域和公共源极区域，以及防止隧道的电介质层图案 。 隧道介电层形成在半导体衬底上。 存储器栅极和选择栅极形成在隧道电介质层上以彼此间隔开。 在存储栅极和选择栅极之间的半导体衬底内形成浮点结区域，与存储栅极相对地形成位线接合区域，并且与浮置结区域相对形成公共源极区域 相对于选择门。 防止隧道的电介质层图案介于半导体衬底和隧穿电介质层之间，并被配置为与存储器栅极的一部分重叠。