公开(公告)号：US08604535B2

公开(公告)日：2013-12-10

申请号：US12648386

申请日：2009-12-29

Applicant: Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L29/788 ,  H01L21/762

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.

Abstract translation: 非易失性存储器件包括其中在衬底中形成晶体管的沟道的有源区，限定有源区的元件隔离膜，并且形成在通道两侧的基底上，高度低于 有源区，第一电介质层，第二电介质层和控制栅电极，以及在第一介电层和第二电介质层之间形成的与栅极的长度相交的浮栅， 通道的方向并延伸到通道两侧的元件隔离膜的上表面，从而围绕通道。

公开(公告)号：US08059473B2

公开(公告)日：2011-11-15

申请号：US12844234

申请日：2010-07-27

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: G11C11/34

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Abstract translation: 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US08053342B2

公开(公告)日：2011-11-08

申请号：US12836066

申请日：2010-07-14

Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC: H01L21/8238

CPC classification number: H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

Abstract translation: 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US07928492B2

公开(公告)日：2011-04-19

申请号：US11804329

申请日：2007-05-17

Applicant: Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

Inventor： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源区。

公开(公告)号：US20100289071A1

公开(公告)日：2010-11-18

申请号：US12844234

申请日：2010-07-27

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Abstract translation: 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US07800158B2

公开(公告)日：2010-09-21

申请号：US11600499

申请日：2006-11-16

Applicant: Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang

Inventor： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang

IPC: H01L31/032

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  Y10S257/90

Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Abstract translation: 提供了一种半导体器件及其形成方法。 半导体器件包括存储器件和自对准选择器件。 在自对准选择装置和存储装置之间形成浮点。

公开(公告)号：US07791951B2

公开(公告)日：2010-09-07

申请号：US12364570

申请日：2009-02-03

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: G11C11/34

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Abstract translation: 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US07696561B2

公开(公告)日：2010-04-13

申请号：US11870762

申请日：2007-10-11

Applicant: Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

Inventor： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract translation: 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

公开(公告)号：US20090141562A1

公开(公告)日：2009-06-04

申请号：US12364570

申请日：2009-02-03

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: G11C16/06 ,  G11C11/34

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Abstract translation: 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US20090121277A1

公开(公告)日：2009-05-14

申请号：US12289297

申请日：2008-10-24

Applicant: Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

Abstract: The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

Abstract translation: 非易失性存储器件包括半导体衬底和限定半导体衬底中的有源区的器件隔离层。 器件隔离层包括比半导体衬底的顶表面低的顶表面，使得有源区的侧上表面被暴露。 感测线与有源区和器件隔离层交叉，并且与感测线间隔开的字线与有源区和器件隔离层交叉。