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    NON-VOLATILE MEMORY AND METHOD OF FABRICATING SAME
    3.
    发明申请
    NON-VOLATILE MEMORY AND METHOD OF FABRICATING SAME 失效
    非易失性存储器及其制造方法

    公开(公告)号：US20080029808A1

    公开(公告)日：2008-02-07

    申请号：US11837361

    申请日：2007-08-10

    Applicant: Hee-Seog JEON ,  Seung-Beom YOON ,  Jeong-Uk HAN

    Inventor： Hee-Seog JEON ,  Seung-Beom YOON ,  Jeong-Uk HAN

    IPC: H01L29/788

    CPC classification number: H01L29/7885 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

    Abstract translation: 在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。 绝缘浮栅设置在基板上。 浮置栅极至少部分地与第一结区重叠。 在浮动门上设置绝缘的程序门。 程序门具有弯曲的上表面。 半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。 擦除栅极部分地与第二结区重叠。

    Method of manufacturing EEPROM cell
    5.
    发明授权
    Method of manufacturing EEPROM cell 失效
    制造EEPROM单元的方法

    公开(公告)号：US07238572B2

    公开(公告)日：2007-07-03

    申请号：US11096038

    申请日：2005-03-31

    Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825

    Abstract: A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.

    Abstract translation: 制造EEPROM单元的方法包括在半导体衬底上生长第一氧化物层; 在所述第一氧化物层上形成第一导电层; 通过图案化所述第一导电层和所述第一氧化物层来形成第一导电图案和隧道氧化物层，所述隧穿氧化物层设置在所述第一导电图案下方; 在所述第一导电图案和所述基板的侧壁上形成栅氧化层，并在所述第一导电图案的两侧上形成第二导电图案; 通过将所述第一导电图案电连接到所述第二导电图案来形成用于浮置栅极的导电层; 在浮栅的导电层上形成耦合氧化物层; 在所述耦合氧化物层上形成第三导电层; 以及通过图案化第三导电层，耦合氧化物层和浮栅的导电层来形成选择晶体管和控制晶体管。 选择晶体管与控制晶体管间隔开。 形成在隧道氧化物层上的选择晶体管包括由选择栅极，第一耦合氧化物图案和第一浮置栅极形成的栅极堆叠，并且控制晶体管包括由控制栅极形成的栅极堆叠， 第二耦合氧化物图案和第二浮栅。

    Self aligned 1 bit local SONOS memory cell
    6.
    发明申请
    Self aligned 1 bit local SONOS memory cell 失效
    自对准1位本地SONOS存储单元

    公开(公告)号：US20070063267A1

    公开(公告)日：2007-03-22

    申请号：US11600765

    申请日：2006-11-17

    Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    Abstract translation: 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    7.
    发明授权
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US07190024B2

    公开(公告)日：2007-03-13

    申请号：US11329217

    申请日：2006-01-10

    Applicant: Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    Inventor： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC: H01L29/788

    CPC classification number: H01L21/28273 ,  H01L21/0214 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/7881

    Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    Abstract translation: 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Method of manufacturing a semiconductor memory device
    8.
    发明授权
    Method of manufacturing a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US07172938B2

    公开(公告)日：2007-02-06

    申请号：US10987340

    申请日：2004-11-12

    Applicant: Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

    Inventor： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

    Abstract translation: 隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。 这些层依次构图。 通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。 在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。 用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

    Split-gate nonvolatile memory device and method of manufacturing the same
    9.
    发明授权
    Split-gate nonvolatile memory device and method of manufacturing the same 有权
    分离式非易失性存储器件及其制造方法

    公开(公告)号：US07160777B2

    公开(公告)日：2007-01-09

    申请号：US10916670

    申请日：2004-08-11

    Applicant: Yong-Suk Choi ,  Seung-Beom Yoon

    Inventor： Yong-Suk Choi ,  Seung-Beom Yoon

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7886 ,  H01L29/7887

    Abstract: Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.

    Abstract translation: 本发明的实施例包括形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上并且彼此分开的间隔物型浮栅和间隔物型图案，浮栅和虚设图案具有面向外的圆形表面; 一对绝缘间隔物，其形成在浮动栅极的侧壁和虚设图案的彼此面对的侧壁上; 在所述一对绝缘间隔件之间以自对准的方式形成的控制栅极; 插入在所述浮动栅极和所述控制栅极之间的隧道绝缘层; 以及在浮置栅极外部的半导体衬底和虚拟图案中形成的源极和漏极区域。

    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same
    10.
    发明授权
    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same 失效
    自对准1位本地SONOS存储单元及其制造方法

    公开(公告)号：US07141473B2

    公开(公告)日：2006-11-28

    申请号：US10912046

    申请日：2004-08-06

    Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    Abstract translation: 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

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