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    Non-volatile semiconductor memory device
    71.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06169690A

    公开(公告)日：2001-01-02

    申请号：US09317238

    申请日：1999-05-24

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C1604

    CPC分类号： G11C16/12 ,  G11C16/0483

    摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the date latch circuits can be formed at any positions remote from the memory cell array.

    摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，将负阈值电压分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，日期锁存电路可以形成在远离存储单元阵列的任何位置处。

    Nonvolatile semiconductor memory device having a matrix of memory cells
    73.
    发明授权
    Nonvolatile semiconductor memory device having a matrix of memory cells 失效
    具有存储单元矩阵的非易失性半导体存储器件

    公开(公告)号：US5877981A

    公开(公告)日：1999-03-02

    申请号：US848226

    申请日：1997-04-29

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

    CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

    摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

    Memory cell of nonvolatile semiconductor memory device
    75.
    发明授权
    Memory cell of nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件的存储单元

    公开(公告)号：US5596525A

    公开(公告)日：1997-01-21

    申请号：US433071

    申请日：1995-05-03

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C11/40

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuits. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

    摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 串联电路在一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

    Semiconductor memory device having redundant memory cells
    76.
    发明授权
    Semiconductor memory device having redundant memory cells 失效
    具有冗余存储单元的半导体存储器件

    公开(公告)号：US5450361A

    公开(公告)日：1995-09-12

    申请号：US197410

    申请日：1994-02-16

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C16/32 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/842 ,  G11C16/28 ,  G11C16/32 ,  G11C7/14

    摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

    摘要翻译： 公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mmn）和对应于存储器单元的两个存储状态的第一参考单元（DM11至DMm1）和第二参考单元（DM12至DMm2），以及 比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储 存储单元的数据。 因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

    Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
    77.
    发明授权
    Electrically programmable nonvolatile semiconductor memory device with NAND cell structure 失效
    具有NAND单元结构的电可编程非易失性半导体存储器件

    公开(公告)号：US5448517A

    公开(公告)日：1995-09-05

    申请号：US288219

    申请日：1994-08-09

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C11/34

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

    摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

    Nonvolatile semiconductor memory device
    78.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5428570A

    公开(公告)日：1995-06-27

    申请号：US67987

    申请日：1993-05-27

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

    CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/26 ,  G11C16/344

    摘要： Memory cells are arrange in the row and column directions in the form of a matrix. A transistor as a load is connected to column lines. A sense amplifier is connected to the transistor. In a read check operation, in which the data in the memory cells are erased, and the erased state of each memory cell is checked, all the row lines are set in a non-selected state by a row decoder, and all the column lines are selected by a column decoder. In this state. the sum of currents flowing in the memory cells is detected by the sense amplifier. When the current detected by the sense amplifier becomes a predetermined value, a data erase operation is ended.

    摘要翻译： 存储单元以矩阵的形式排列在行和列方向上。 作为负载的晶体管连接到列线。 感测放大器连接到晶体管。 在检查存储单元中的数据被擦除并且检查每个存储单元的擦除状态的读取检查操作中，行解码器将所有行线设置为非选择状态，并且所有列线 由列解码器选择。 在这种状态 在存储单元中流动的电流的总和由读出放大器检测。 当由读出放大器检测到的电流变为预定值时，数据擦除操作结束。

    Semiconductor memory device
    79.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5321655A

    公开(公告)日：1994-06-14

    申请号：US111050

    申请日：1993-08-24

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C16/32 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/842 ,  G11C16/28 ,  G11C16/32 ,  G11C7/14

    摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

    摘要翻译： 公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mnn）和与存储器单元的相应两个存储状态对应的第一参考单元（DM11至Dm1）和第二参考单元（DM12至DMm2），以及 比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储 存储单元的数据。 因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

    Semiconductor integrated circuit
    80.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5200926A

    公开(公告)日：1993-04-06

    申请号：US722530

    申请日：1991-06-27

    申请人： Hiroshi Iwahashi ,  Hideo Kato ,  Yuuichi Tatsumi

    发明人： Hiroshi Iwahashi ,  Hideo Kato ,  Yuuichi Tatsumi

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C7/1006 ,  G11C7/22 ,  G11C8/18

    摘要： A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

    摘要翻译： 数据传输控制电路连接在读出放大器和输出缓冲电路之间。 数据传送控制电路由脉冲信号发生器提供的脉冲信号控制，具有较长的延迟时间，该脉冲信号不由脉冲信号发生器产生，作为噪声消除器进行操作，并防止从其输出错误信号 输出缓冲电路。