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    Expandable queue
    61.
    发明授权
    Expandable queue 有权

    公开(公告)号：US11558309B1

    公开(公告)日：2023-01-17

    申请号：US17369992

    申请日：2021-07-08

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo

    IPC: H04L47/625 ,  H04L49/90 ,  H04L49/9005 ,  H04L47/62

    Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING INFORMATION PROCESSING PROGRAM
    62.
    发明申请
    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING INFORMATION PROCESSING PROGRAM 有权

    公开(公告)号：US20220368644A1

    公开(公告)日：2022-11-17

    申请号：US17702332

    申请日：2022-03-23

    Applicant: FUJITSU LIMITED

    Inventor： Jun KATO

    IPC: H04L47/41 ,  H04L47/2441 ,  H04L47/27 ,  H04L49/9005

    Abstract: An information processing apparatus including: a memory; and a processor coupled to the memory, the processor being configured to perform processing including: executing a buffer management processing that, under flow control over communication executed by an arithmetic processing device, sequentially obtains a plurality of packets transmitted and destined for the arithmetic processing device, stores the packets in a buffer, generates one aggregated packet by aggregating the packets, and transmits the aggregated packet to the arithmetic processing device; executing an ACK management processing that decides transmission timing for ACKs to a transmission source of the packets based on a flow rate for the aggregated packet; and executing a window management processing that decides a receive window size representing a data amount to be transmitted by one flow to the arithmetic processing device based on the flow rate for the aggregated packet.

    STREAMING COMMUNICATION BETWEEN DEVICES
    65.
    发明申请
    STREAMING COMMUNICATION BETWEEN DEVICES 有权

    公开(公告)号：US20220217098A1

    公开(公告)日：2022-07-07

    申请号：US17606715

    申请日：2020-04-02

    Applicant: Microsoft Technology Licensing, LLC

    Inventor： Zhixiong Niu ,  Ran Shu ,  Lei Qu ,  Peng Chen ,  Yongqiang Xiong ,  Guo Chen

    IPC: H04L49/102 ,  H04L49/9005 ,  H04L49/90 ,  H04L67/1097

    Abstract: In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.

    DATA ACCESS TECHNOLOGIES
    66.
    发明申请
    DATA ACCESS TECHNOLOGIES 有权

    公开(公告)号：US20220210097A1

    公开(公告)日：2022-06-30

    申请号：US17477782

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Ziye YANG

    IPC: H04L49/90 ,  H04L49/103 ,  H04L49/9005 ,  H04L9/40 ,  H04L67/1097

    Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: cause a first number of processors of the at least one processor to access queues exclusively allocated for packets to be processed by the first number of processors; cause a second number of processors of the at least one processor to identify commands consistent with Non-volatile Memory Express (NVMe) over Quick User Data Protocol Internet Connections (QUIC), wherein the commands are received in the packets and the second number is based at least in part on a rate of received commands; and cause performance of the commands using a third number of processors. In some examples, the circuitry, when operational, is to: based on detection of a new connection on a first port, associate the new connection with a second port, wherein the second port is different than the first port and select at least one processor to identify and process commands received on the new connection.

    Queue pacing in a network device
    67.
    发明授权
    Queue pacing in a network device 有权

    公开(公告)号：US12231342B1

    公开(公告)日：2025-02-18

    申请号：US18117290

    申请日：2023-03-03

    Applicant: Marvell Asia Pte Ltd

    Inventor： Bruce Kwan ,  William Brad Matthews

    IPC: H04L47/25 ,  H04L47/11 ,  H04L47/62 ,  H04L49/9005

    Abstract: A network device includes ingress queues for storing data units while the data units are being processed by ingress packet processors, and a plurality of egress buffer memories for storing data units received from the ingress queues while the data units are being processed by the egress packet processors. First circuitry controls respective rates at which data units are transferred from ingress queues to egress buffer memories. Second circuitry monitors the egress buffer memories for congestion and sends, to the first circuitry, flow control messages related to congestion resulting of egress buffer memories. The first circuitry progressively increases over time a rate at which data from each ingress queue are transferred to an egress buffer memory in response to receiving a flow control message that indicates that congestion corresponding to the egress buffer memory has ended.

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