公开(公告)号：US4897150A

公开(公告)日：1990-01-30

申请号：US213146

申请日：1988-06-29

Applicant: Daniel J. Dooley ,  Arthur R. Elsea, Jr.

Inventor： Daniel J. Dooley ,  Arthur R. Elsea, Jr.

IPC: H01L21/3205 ,  H01L21/321

CPC classification number: H01L21/321 ,  H01L21/32051 ,  Y10S438/903 ,  Y10S438/98

Abstract: An improved method of patterning a conductive interconnect on a semiconductor element is disclosed. A catalytic layer of, for example, amorphous silicon is deposited on a semiconductor element. The areas over which a conductive pattern is to be formed is activated by directing a focused laser beam onto the amorphous silicon to form crystallized silicon. The amorphous silicon is then etched away after which a conductive material such as a metal is deposited on the activated crystallized silicon.

公开(公告)号：US4849071A

公开(公告)日：1989-07-18

申请号：US131058

申请日：1987-12-09

Applicant: Alan G. R. Evans ,  Mohammed M. Farooqui

Inventor： Alan G. R. Evans ,  Mohammed M. Farooqui

IPC: G01L9/00 ,  H04R7/02 ,  H04R19/00

CPC classification number: H04R19/00 ,  G01L9/0042 ,  G01L9/0073 ,  H04R7/02 ,  Y10S438/98 ,  Y10T29/49103

Abstract: The invention provides a method of forming a sealed diaphragm (3) on a substrate (1) which comprises providing on the substrate (1) a sacrificial layer (2) , providing a diaphragm layer (3) over the sacrificial layer (2), providing at least one aperture (5) in the diaphragm layer (3) which is spaced from the periphery of the diaphragm layer (3), at least partially removing the sacrificial layer (2) from between the substrate (1) and the diaphragm layer (3) by way of the at least one aperture (5) and closing the at least one aperture (5).

Abstract translation: 本发明提供了一种在衬底（1）上形成密封隔膜（3）的方法，该方法包括在衬底（1）上设置牺牲层（2），在牺牲层（2）上提供隔膜层（3） 在所述隔膜层（3）中设置与所述隔膜层（3）的周边隔开的至少一个孔（5），至少部分地从所述基板（1）和所述隔膜层（3）之间移除所述牺牲层（2） （3）通过所述至少一个孔（5）并且关闭所述至少一个孔（5）。

公开(公告)号：US4818712A

公开(公告)日：1989-04-04

申请号：US107626

申请日：1987-10-13

Applicant: John W. Tully

Inventor： John W. Tully

IPC: H01L21/331 ,  H01L21/88 ,  H01L21/306

CPC classification number: H01L29/66272 ,  H01L29/66318 ,  Y10S148/01 ,  Y10S148/056 ,  Y10S148/084 ,  Y10S148/10 ,  Y10S438/951 ,  Y10S438/98

Abstract: An aluminum liftoff masking process is effected on a prepared gallium arsenide wafer having a base thereon. Successive layers of silicon dioxide and aluminum are deposited on the wafer. The aluminum and silicon dioxide layers are successively etched, including undercutting of the aluminum layer. Base majority carriers are implanted through the windows to the base and refractory metal ohmic contacts are built up in the windows. After forming the base contacts, the base contact areas may be passivated. The aluminum layer and any overlaying layers thereon are removed by etching off the aluminum.

Abstract translation: 在其上具有基底的制备的砷化镓晶片上进行铝剥离掩模工艺。 二氧化硅和铝的连续层沉积在晶片上。 铝和二氧化硅层被连续蚀刻，包括铝层的底切。 基底多数载体通过窗口植入基部，难熔金属欧姆接触件在窗户中建成。 在形成基底触点之后，可以钝化基部接触区域。 铝层和其上的任何覆盖层通过蚀刻掉铝来去除。

公开(公告)号：US4729965A

公开(公告)日：1988-03-08

申请号：US855616

申请日：1986-04-09

Applicant: Yoichi Tamaki ,  Kazuhiko Sagara ,  Norio Hasegawa ,  Shinji Okazaki ,  Toshihiko Takakura ,  Hirotaka Nishizawa

Inventor： Yoichi Tamaki ,  Kazuhiko Sagara ,  Norio Hasegawa ,  Shinji Okazaki ,  Toshihiko Takakura ,  Hirotaka Nishizawa

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L27/12 ,  H01L21/265

CPC classification number: H01L21/033 ,  H01L21/28525 ,  H01L29/0804 ,  Y10S438/98

Abstract: This invention relates to a method of producing a semiconductor device which is suitable for forming a bipolar transistor having less fluctuation of characteristics at a high production yield.In accordance with the present invention, a graft base (or an extrinsic base) 20 is formed by doping an impurity from a polycrystalline silicon film 13, while an emitter is formed by lithographic technique.Since the emitter is formed by lithographic technique, the position at which the emitter is to be formed unavoidably changes at the time of mask alignment, but its influence upon transistor characteristics is negligible. Therefore, bipolar transistors having far more uniform characteristics can be formed far more easily than with the method which forms the emitter by self-alignment.

Abstract translation: PCT No.PCT / JP85 / 00432 Sec。 371日期：1986年4月9日 102（e）日期1986年4月9日PCT提交1985年7月31日PCT公布。 第WO86 / 01338号公报 日期：1986年2月27日。本发明涉及一种制造半导体器件的方法，该半导体器件适于形成具有较低产量波动特性的双极晶体管，其产率高。 根据本发明，通过从多晶硅膜13掺杂杂质形成移植物基底（或非本征基底）20，同时通过光刻技术形成发射体。 由于发射极是通过光刻技术形成的，因此在掩模取向时发射极的形成位置不可避免地会发生变化，但是它对晶体管特性的影响可以忽略不计。 因此，与通过自对准形成发射极的方法相比，可以形成具有更均匀特性的双极晶体管。

公开(公告)号：US4560421A

公开(公告)日：1985-12-24

申请号：US307877

申请日：1981-10-02

Applicant: Satoshi Maeda ,  Hiroshi Iwai

Inventor： Satoshi Maeda ,  Hiroshi Iwai

IPC: H01L21/20 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/0638 ,  H01L21/76294 ,  Y10S438/98

Abstract: Disclosed is a method of manufacturing a semiconductor device comprising a step of forming a field region formation insulating film on a semiconductor substrate, a step of forming a mask pattern covering a portion of the insulating film corresponding to an intended element region, a step of ion implanting a field inversion prevention impurity into an element isolation region of the substrate with the mask pattern used as a shield, a step of forming an etching-proof layer on a portion of the insulating film corresponding to a field region, a step of removing the mask pattern to let an etching-proof layer portion be left on the intended element isolation region, and a step of selectively etching the insulating film with the remaining etching-proof layer used as a mask to form the element isolation region. Also disclosed is a semiconductor device manufactured by making use of this method.

Abstract translation: 公开了一种制造半导体器件的方法，包括在半导体衬底上形成场区形成绝缘膜的步骤，形成覆盖与期望元件区域相对应的绝缘膜的一部分的掩模图案的步骤，离子的步骤 将掩膜图案用作屏蔽，将场反转防止杂质注入到衬底的元件隔离区中，在对应于场区的绝缘膜的一部分上形成耐蚀刻层的步骤， 掩模图案，使防腐蚀层部分留在所要的元件隔离区域上;以及使用剩余的防腐蚀层作为掩模选择性地蚀刻绝缘膜的步骤以形成元件隔离区域。 还公开了通过使用该方法制造的半导体器件。

公开(公告)号：US4528744A

公开(公告)日：1985-07-16

申请号：US482229

申请日：1983-04-05

Applicant: Tadashi Shibata

Inventor： Tadashi Shibata

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L21/88

CPC classification number: H01L23/535 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S438/98

Abstract: A method of manufacturing a semiconductor device which comprises the steps of forming an interconnection layer through an insulating film on a semiconductor substrate, and connecting the diffusion interconnection region in the surface portion of said substrate to said interconnection layer by growing a metal or metal semiconductor compound on the surface of said substrate and the interconnection layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：通过半导体衬底上的绝缘膜形成互连层，并通过生长金属或金属半导体化合物将所述衬底的表面部分中的扩散互连区域连接到所述互连层 在所述基板和互连层的表面上。

公开(公告)号：US3877051A

公开(公告)日：1975-04-08

申请号：US29872972

申请日：1972-10-18

Applicant: IBM

Inventor： CALHOUN HARRY C ,  FREED LARRY E ,  KAUFMAN CARL L

IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L19/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/98 ,  H01L2924/00

Abstract: A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.

Abstract translation: 一种平面半导体集成电路芯片结构，其包含不同类型和多个导电性确定杂质的多个区域从该平面表面延伸到芯片中以提供该电路的有源和无源器件。 表面被绝缘结构钝化，其中包含至少两层的金属化图案，用于将形成在第一层上的集成电路器件和穿过第二层或上层的通孔与该金属化图案的各个部分接触。 通孔布置成使得大部分孔布置在具有这样的杂质类型和浓度的表面区域上方，该杂质类型和浓度将与形成在所述通孔中的触点的金属形成肖特基势垒接触。 因此，如果在通过蚀刻通过第二层形成通路孔期间，伴随着进一步的蚀刻通过第一层到半导体区域的表面，所述区域将与沉积在通孔中的金属形成肖特基势垒接触 该接触件将起作用以防止金属化和表面区域之间的短路。

公开(公告)号：US3825450A

公开(公告)日：1974-07-23

申请号：US24940372

申请日：1972-05-01

Applicant: MOTOROLA INC

Inventor： SCHOEFF J

IPC: H01L21/763 ,  H01L21/8222 ,  H01L29/08 ,  B44D1/18 ,  H01L7/36 ,  H01L19/00

CPC classification number: H01L29/0821 ,  H01L21/763 ,  H01L21/8222 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S438/98

Abstract: THE LAYER OF SEMICONDUCTOR MATERIAL UPON WHICH IT IS DEPOSITED BUT OPPOSITE THAT OF THE STRUCTURE TO BE ISOLATED, IT FORMS A GOOD ISOLATION MEMBER. VARIOUS PROCESSES ARE SHOWN FOR ADVANTAGEOUSLY FASHIONING POLYCRYSTALLINE SILICON STRUCTURES.

AN IMPROVED INTEFRATED CIRCUIT STRUCTURE IS SHOWN HAVING AN INTEGRAL POLYCRYSTALLINE SILICON MEMBER. THE DOPING OF SUCH POLYCRYSTALLINE SILICON MEMBER CONTROLS TTHE USAGE OF SUCH MEMBER. WHEN THE POLY SILICON DOPING CHARACTERISTICS EQUAL THAT OF THE LAYER OF SEMICONDUCTOR MATERIAL UPON WHICH IT IS DEPOSITED, IT FORMS A GOOD CONDUCTOR AND IS USABLE AS A CONTACT. WHEN THE POLYCRYSTALLINE SILICON DOPING CHARACTERISTICS ARE AGAIN THE SAME AS THAT OF

公开(公告)号：US3798082A

公开(公告)日：1974-03-19

申请号：US3798082D

申请日：1972-08-07

Applicant: BELL TELEPHONE LABOR INC

Inventor： SCHWARTZ B

IPC: H01L21/00 ,  H01L21/288 ,  H01L23/29 ,  H01L7/34

CPC classification number: H01L21/00 ,  H01L21/288 ,  H01L23/29 ,  H01L2924/0002 ,  Y10S148/065 ,  Y10S438/98 ,  H01L2924/00

Abstract: A passivated p-n junction device in which the junction is prevented from rising to the crystallographic surface by the interposition of a semi-insulating layer intermediate the crystallographic surface and the electrical surface is described. The structure is fabricated by forming a semi-insulating layer upon the surface of an n-type Group III(a) - V(a) compound semiconductor, generating a window therein and introducing a ptype material through the window.

Abstract translation: 描述了通过在晶体表面和电气表面之间插入半绝缘层来防止结被上升到结晶表面的钝化p-n结器件。 通过在n型III（a）-V（a）化合物半导体的表面上形成半绝缘层，在其中产生窗口并通过窗口引入p型材料来制造该结构。

公开(公告)号：US3667115A

公开(公告)日：1972-06-06

申请号：US82387669

申请日：1969-05-12

Applicant: IBM

Inventor： BARSON FRED ,  LEHMAN HERBERT S

IPC: H01L21/8236 ,  H01L23/29 ,  H01L27/00 ,  H01L27/07 ,  H01L29/00 ,  H01L29/78 ,  B01J17/00 ,  H01G13/00

CPC classification number: H01L29/7816 ,  H01L21/8236 ,  H01L23/291 ,  H01L27/00 ,  H01L27/0716 ,  H01L29/7838 ,  H01L2924/0002 ,  Y10S148/053 ,  Y10S148/145 ,  Y10S148/167 ,  Y10S438/92 ,  Y10S438/98 ,  H01L2924/00

Abstract: A method for forming a semiconductor device having a substantially cup-shaped region of one conductivity type between two regions of opposite conductivity type to preferably form a field effect transistor device. The region may be formed through one opening in an insulating layer located upon the surface of the device. Two successive diffusion operations of opposite conductivity types made through this same opening in the insulating layer forms the cup-shaped region to the desired thickness.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件具有在相反导电类型的两个区域之间具有一种导电类型的大致杯状区域，以优选形成场效应晶体管器件。 该区域可以通过位于设备表面上的绝缘层中的一个开口形成。 在绝缘层中通过相同的开口形成的相反导电类型的两个连续的扩散操作形成了杯形区域至所需的厚度。