公开(公告)号：US3922707A

公开(公告)日：1975-11-25

申请号：US47787174

申请日：1974-06-10

Applicant: IBM

Inventor： FREED LARRY E ,  NESTORK WILLIAM J ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L27/04

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L27/0755 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/136

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

Abstract translation: 在包括通过导电装置互连成选定电路配置的多个有源和无源器件的集成半导体电路中，改进之处在于，其中所述电路配置被布置为没有显示电抗的可能路径，该电抗将替代所选择的基本上无电阻的路径 在所述无电阻通路中的一个结构故障的情况下在关键电路节点中，由此集成电路的DC测试不受这种替代路径的影响。

公开(公告)号：US3877051A

公开(公告)日：1975-04-08

申请号：US29872972

申请日：1972-10-18

Applicant: IBM

Inventor： CALHOUN HARRY C ,  FREED LARRY E ,  KAUFMAN CARL L

IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L19/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/98 ,  H01L2924/00

Abstract: A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.

Abstract translation: 一种平面半导体集成电路芯片结构，其包含不同类型和多个导电性确定杂质的多个区域从该平面表面延伸到芯片中以提供该电路的有源和无源器件。 表面被绝缘结构钝化，其中包含至少两层的金属化图案，用于将形成在第一层上的集成电路器件和穿过第二层或上层的通孔与该金属化图案的各个部分接触。 通孔布置成使得大部分孔布置在具有这样的杂质类型和浓度的表面区域上方，该杂质类型和浓度将与形成在所述通孔中的触点的金属形成肖特基势垒接触。 因此，如果在通过蚀刻通过第二层形成通路孔期间，伴随着进一步的蚀刻通过第一层到半导体区域的表面，所述区域将与沉积在通孔中的金属形成肖特基势垒接触 该接触件将起作用以防止金属化和表面区域之间的短路。