公开(公告)号：US2993999A

公开(公告)日：1961-07-25

申请号：US84988559

申请日：1959-10-30

Applicant: IBM

Inventor： CASMIR KAY ,  MCMURTRIE JOHN S ,  NESTORK WILLIAM J ,  STURTEVANT VERNON O

公开(公告)号：US3922707A

公开(公告)日：1975-11-25

申请号：US47787174

申请日：1974-06-10

Applicant: IBM

Inventor： FREED LARRY E ,  NESTORK WILLIAM J ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L27/04

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L27/0755 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/136

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

Abstract translation: 在包括通过导电装置互连成选定电路配置的多个有源和无源器件的集成半导体电路中，改进之处在于，其中所述电路配置被布置为没有显示电抗的可能路径，该电抗将替代所选择的基本上无电阻的路径 在所述无电阻通路中的一个结构故障的情况下在关键电路节点中，由此集成电路的DC测试不受这种替代路径的影响。