公开(公告)号：US3689803A

公开(公告)日：1972-09-05

申请号：US3689803D

申请日：1971-03-30

Applicant: IBM

Inventor： BAKER THEODORE H ,  TUMAN DANIEL

IPC: H01L21/00 ,  H01L27/02 ,  H01L27/118 ,  H01L19/00

CPC classification number: H01L27/11801 ,  H01L21/00 ,  H01L27/0207

Abstract: A planar monolithic integrated circuit chip containing an isolation region of one conductivity type extending completely around the edge or periphery of the chip in order to insure that there are no exposed P-N junctions on an edge surface of the chip. Such an isolation region extends for at least a minimum distance from the edge of the chip, said distance being determined so as to minimize the risk of any edge defects in the chip resulting from dicing and handling from extending beyond the isolation region into the body of the chip. An insulative layer over the planar surface of the chip supports a metallization pattern for interconnecting the devices in the integrated circuit and for distributing a plurality of voltage supplys at different levels to the devices. The metallization pattern is arranged so that only metallization connected to the voltage supply at the same level as the peripheral isolation region is located on the portion of the insulative layer between the chip edge and the minimum distance of the isolation junction from the edge.

Abstract translation: 一种平面单片集成电路芯片，其包含完全绕芯片的边缘或周边延伸的一种导电类型的隔离区域，以确保在芯片的边缘表​​面上没有暴露的P-N结。 这种隔离区域延伸至少距离芯片边缘的最小距离，所述距离被确定为使由切割和处理引起的芯片中的任何边缘缺陷的风险最小化，从而延伸超出隔离区域进入体内 芯片。 在芯片的平面表面上的绝缘层支持用于互连集成电路中的器件的金属化图案，并用于将不同电平的多个电压源分配到器件。 金属化图案被布置为使得只有与外围隔离区域相同电平的电压源的金属化位于芯片边缘与隔离结与边缘的最小距离之间的绝缘层的部分上。

公开(公告)号：US3922707A

公开(公告)日：1975-11-25

申请号：US47787174

申请日：1974-06-10

Applicant: IBM

Inventor： FREED LARRY E ,  NESTORK WILLIAM J ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L27/04

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L27/0755 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/136

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

Abstract translation: 在包括通过导电装置互连成选定电路配置的多个有源和无源器件的集成半导体电路中，改进之处在于，其中所述电路配置被布置为没有显示电抗的可能路径，该电抗将替代所选择的基本上无电阻的路径 在所述无电阻通路中的一个结构故障的情况下在关键电路节点中，由此集成电路的DC测试不受这种替代路径的影响。