公开(公告)号：US06352203B1

公开(公告)日：2002-03-05

申请号：US09270691

申请日：1999-03-17

Applicant: Jim W. Brainard ,  Eric M. Monsef

Inventor： Jim W. Brainard ,  Eric M. Monsef

IPC: G06K708

CPC classification number: H01L23/34 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H05K1/0266 ,  H05K1/14 ,  H05K2201/09927 ,  H05K2201/10151 ,  H05K2201/10689 ,  H01L2924/00

Abstract: An apparatus is used to identify the type of microprocessor assembly mounted on a printed circuit board. A heat sink is coupled to the microprocessor assembly, and a label is coupled to the heat sink. The label has one of a plurality of preselected patterns of optically reflective and non-reflective areas formed thereon, and at least one photodetector is positioned adjacent the microprocessor assembly on the printed circuit board for detecting the preselected pattern.

Abstract translation: 一种装置用于识别安装在印刷电路板上的微处理器组件的类型。 散热器耦合到微处理器组件，并且标签耦合到散热器。 该标签具有形成在其上的光反射区域和非反射区域的多个预选图案中的一个，并且至少一个光电检测器与印刷电路板上的微处理器组件相邻定位，用于检测预选图案。

公开(公告)号：US5886875A

公开(公告)日：1999-03-23

申请号：US581860

申请日：1996-01-02

Applicant: William C. Phelps, III ,  John M. Heffernan ,  Habib Amirzadeh

Inventor： William C. Phelps, III ,  John M. Heffernan ,  Habib Amirzadeh

IPC: H05K1/02 ,  H05K3/00 ,  H05K5/00

CPC classification number: H05K3/0052 ,  H05K1/0266 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/09927 ,  H05K2203/0191

Abstract: A circuit board (10) has a frangible portion (12) for carrying information relating to the circuitry carried on the circuit board. The information is carried in the form of a label (18) or barcode, and identifies the version of the circuitry so that during manufacturing, and later during repair, the circuit can be correctly identified. The frangible portion is broken from the circuit board, but kept with the circuit board. In one embodiment, an adhesive label retains the frangible portion.

Abstract translation: 电路板（10）具有用于承载与电路板上承载的电路有关的信息的易碎部分（12）。 信息以标签（18）或条形码的形式携带，并且识别电路的版本，使得在制造期间以及在修复期间可以正确识别电路。 易碎部分与电路板断开，但与电路板保持一致。 在一个实施例中，粘合标签保持易碎部分。

公开(公告)号：US5614698A

公开(公告)日：1997-03-25

申请号：US374315

申请日：1995-01-17

Applicant: H. Scott Estes

Inventor： H. Scott Estes

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0266 ,  H05K2201/0919 ,  H05K2201/09927 ,  H05K3/4641 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: The substrate member of a multi-tier circuit board is provided, during the construction thereof, with an integral bar code structure by extending spaced apart, parallel finger sections of an interior metal ground plane portion of a panel structure outwardly past the routing path along which the substrate member is to be separated from the panel structure. After the substrate member is routed from the panel structure it has a peripheral side edge portion upon which exposed end surface portions of the spaced ground plane finger sections are disposed in a mutually spaced bar code array representative of predetermined information relating to the completed circuit board. The ground-seeking probe portion of a conductive scanning device is moved along the bar-coded edge of the substrate member to read and decipher the integral ground plane bar code structure compactly incorporated thereon during the manufacture of the substrate member.

Abstract translation: 多层电路板的基板构件在其构造期间通过将面板结构的内部金属接地平面部分的间隔开的平行指部分向外延伸穿过路径路径而设置在整个条形码结构中 衬底构件将与面板结构分离。 在基板构件从面板结构布线之后，其具有外围侧边缘部分，间隔开的接地平面指状部分的露出端表面部分布置在表示与完成的电路板有关的预定信息的相互间隔的条形码阵列中。 导电扫描装置的寻址探针部分沿着基板构件的条形边缘移动，以读取和解密在制造基板构件期间紧凑地结合在其上的整体接地平面条形码结构。

公开(公告)号：US5528825A

公开(公告)日：1996-06-25

申请号：US447829

申请日：1995-05-23

Applicant: Kazuo Miyauchi ,  Kazuya Sunami ,  Kohei Mandai ,  Takako Higuchi

Inventor： Kazuo Miyauchi ,  Kazuya Sunami ,  Kohei Mandai ,  Takako Higuchi

IPC: H05K13/02 ,  H01L21/98 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H05K13/08 ,  H05K3/30

CPC classification number: H01L25/50 ,  H01L23/544 ,  H05K1/0266 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H05K1/18 ,  H05K2201/09927 ,  H05K2201/10689 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/53022 ,  Y10T29/53061 ,  Y10T29/53091 ,  Y10T29/53178 ,  Y10T29/53183

Abstract: A system for manufacturing a hybrid integrated circuit by mounting an IC and a chip component on a circuit substrate. The system comprises a bar code reader for reading the characteristic data of each IC shown previously thereon to indicate the characteristic thereof, and a selector for selecting an optimal chip component in accordance with the read characteristic of the IC, thereby achieving manufacture of a satisfactory hybrid integrated circuit having predetermined performance.

Abstract translation: 一种用于通过将IC和芯片组件安装在电路基板上来制造混合集成电路的系统。 该系统包括条形码阅读器，用于读取其前面所示的每个IC的特征数据以指示其特征;以及选择器，用于根据IC的读取特性选择最佳芯片组件，从而实现令人满意的混合 集成电路具有预定的性能。

公开(公告)号：US5260168A

公开(公告)日：1993-11-09

申请号：US902418

申请日：1992-06-19

Applicant: Robert D. Vernon

Inventor： Robert D. Vernon

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  G03C5/00

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/544 ,  H05K3/0082 ,  H01L2223/54473 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2203/0195 ,  H05K2203/0505 ,  H05K2203/0551 ,  H05K2203/107 ,  H05K2203/1545 ,  H05K3/064 ,  Y10T29/49121 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T428/14 ,  Y10T428/1486 ,  Y10T428/24322

Abstract: A method for patterning a tape to which an integrated circuit may be bonded including providing a tape having a top layer of unexposed film which, when exposed in an interconnection pattern and developed, acts as a mask for processing a photoprocessable layer of the tape to provide conductive portions in an interconnection pattern on the tape.

Abstract translation: 一种用于图案化可以结合集成电路的带的方法，包括提供具有未曝光膜顶层的带，当以互连图案曝光并显影时，其作为用于处理带的可光处理层的掩模，以提供 磁带上的互连图案中的导电部分。

公开(公告)号：US5067229A

公开(公告)日：1991-11-26

申请号：US601934

申请日：1990-10-22

Applicant: Nobuyuki Nakamura

Inventor： Nobuyuki Nakamura

IPC: B23C3/28 ,  B23C1/06 ,  B23C3/00 ,  B24B27/06 ,  G09F3/00 ,  H01L25/075 ,  H05K1/02 ,  H05K3/00

CPC classification number: G09F3/00 ,  H01L25/0753 ,  H05K1/0266 ,  H05K3/0052 ,  H01L2924/0002 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/10106 ,  H05K2203/1545 ,  Y10T29/49121 ,  Y10T29/5148 ,  Y10T409/307 ,  Y10T409/307112 ,  Y10T409/30924

Abstract: The present invention provides a method of producing electronic components such as LED displays and hybrid IC's from a board supply frame. The frame comprises a parallel pair of elongate side bands, and a plurality of unit circuit boards integrally incorporated in the frame by means of connecting webs and arranged between the pair of side bands at a predetermined interval therealong. Various process steps such as chip bonding and wire bonding are performed with respect to the individual circuit boards while they are still in the frame. In a final step, each unit circuit board or electronic component is separated from the frame. The frame may be provided with an identification pattern to identify the type of unit circuit boards incorporated in the frame.

Abstract translation: 本发明提供一种从电路板供给框架制造诸如LED显示器和混合IC的电子部件的方法。 该框架包括平行的一对细长边带，以及多个单元电路板，其通过连接腹板一体地结合在框架中，并且以一定间隔在该对边带之间布置。 当各个电路板仍在框架中时，执行诸如芯片接合和引线键合的各种工艺步骤。 在最后一步中，每个单元电路板或电子部件与框架分离。 该框架可以设置有识别图案，以识别结合在框架中的单元电路板的类型。

公开(公告)号：US4756929A

公开(公告)日：1988-07-12

申请号：US681686

申请日：1984-12-14

Applicant: Donald F. Sullivan

Inventor： Donald F. Sullivan

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  H05K3/46 ,  B05D5/12 ,  G03C5/00 ,  H05K1/00 ,  H05K3/02

CPC classification number: H05K3/107 ,  H05K3/184 ,  H05K3/242 ,  H05K3/3452 ,  H05K1/117 ,  H05K2201/09036 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/09981 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/056 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/066 ,  H05K2203/0759 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/108 ,  H05K3/4661 ,  Y10T29/49155

Abstract: Densely packed high resolution printed wiring boards may be achieved by providing channels below grade in a substrate planar surface, thereby providing greater conductor width for closely spaced conductors. By mechanically removing the substrate surface between the channels, high virtual resolution is obtained with high quality conductors and insulation spacings of the order of about 0.003 inch, and with actual conductor widths of greater than 0.012 inch. Thus the packing density of printed wiring patterns may be increased significantly. Also the quality of conductor adherence and conductivity is improved. Thus a non-critical and inexpensive process unexpectedly provides an improved quality, more precise printed wiring pattern.

Abstract translation: 密集的高分辨率印刷线路板可以通过在基板平面中提供低于等级的通道，从而为紧密间隔的导体提供更大的导体宽度。 通过机械地去除通道之间的基板表面，可以获得具有约0.003英寸量级的高质量导体和绝缘间距以及大于0.012英寸的实际导体宽度的高虚拟分辨率。 因此，可以显着地增加印刷布线图案的包装密度。 导体粘附性和导电性也提高了。 因此，非关键和廉价的工艺意外地提供了改进的质量，更精确的印刷布线图案。

公开(公告)号：US4582987A

公开(公告)日：1986-04-15

申请号：US500019

申请日：1983-06-01

Applicant: James S. Bianco

Inventor： James S. Bianco

IPC: G06K19/02 ,  G09F3/18 ,  H05K1/02 ,  G06K7/00

CPC classification number: H05K1/0266 ,  G06K19/02 ,  G09F3/18 ,  H05K2201/09927 ,  H05K2201/10606 ,  H05K2203/0191

Abstract: A bar coded index tab for affixation of a label to an article. The tab has a base (60) including a front face (70) and a notch (80) extending across the front face for affixing thereto a label (20) having machine-readable bar coded information on a portion of the label and human-readable information on another portion of the label. The machine-readable information is read in one portion of the notch and the human-readable information is read in another portion of the notch. Lips (110A and 110B) are provided along each side of the notch to grip the label. The reading instrument is located against one of the lips for movement along the lip to accurately read the bar code information without the necessity for human visual contact with the label. The tab has means (120) for attaching the base to an object to be labelled.

Abstract translation: 用于将标签贴到物品上的条形码索引标签。 突片具有基部（60），其包括前表面（70）和延伸穿过前表面的凹口（80），用于将标签（20）附接到标签的一部分上的机器可读条形码信息， 标签的另一部分的可读信息。 在凹口的一部分中读取机器可读信息，并且在凹口的另一部分中读取人可读信息。 沿着凹口的每一侧设置嘴（110A和110B）以夹紧标签。 读数仪器位于一个嘴唇上，用于沿唇缘移动，以准确地读取条形码信息，而不需要与标签进行人类视觉接触。 突片具有用于将基座附接到待标记物体的装置（120）。

公开(公告)号：US20240244742A1

公开(公告)日：2024-07-18

申请号：US18559498

申请日：2022-01-28

Applicant: NITTO DENKO CORPORATION

Inventor： Kenya TAKIMOTO ,  Naoki SHIBATA ,  Hayato TAKAKURA

IPC: H05K1/02 ,  H05K1/05

CPC classification number: H05K1/0296 ,  H05K1/05 ,  H05K2201/09927

Abstract: A wiring circuit board includes a support metal layer; a base insulating layer disposed on at least one surface in the thickness direction of the support metal layer, and a wiring layer disposed on one surface in the thickness direction of the base insulating layer. A plurality of stripe grooves that extends along a predetermined direction orthogonal to the thickness direction and a plurality of recesses that sinks in the thickness direction of the support metal layer are formed on one surface in the thickness direction and/or the other surface in the thickness direction of the support metal layer. The recesses form a two-dimensional code having a generally rectangular shape in plan view by means of a dot pattern. One side of the two-dimensional code is disposed so as to lie along the stripe grooves.

公开(公告)号：US11937369B2

公开(公告)日：2024-03-19

申请号：US15733672

申请日：2019-03-28

Applicant: AT&S (China) Co. Ltd.

Inventor： Seok Kim Tay ,  Azmi Ibrahim ,  Wenping Dai ,  Chunjie Shen

IPC: G06K19/06 ,  G06K7/14 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0268 ,  G06K7/1413 ,  G06K19/06028 ,  H05K1/0269 ,  H05K3/0005 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2203/163

Abstract: A component carrier related body which includes a stack with a plurality of electrically conductive and/or electrically insulating layer structures, and at least two information carrying structures formed vertically displaced on at least two different of the layer structures, wherein at least two of the at least two information carrying structures are laterally displaced in a plan view on the stack.