公开(公告)号：US07850087B2

公开(公告)日：2010-12-14

申请号：US11176326

申请日：2005-07-08

Applicant: Yi-sung Hwang ,  Sung-dae Cho

Inventor： Yi-sung Hwang ,  Sung-dae Cho

IPC: G06K19/06 ,  G06K19/00

CPC classification number: H05K1/117 ,  G06K19/07732 ,  G06K19/07743 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/141 ,  H05K2201/043 ,  H05K2201/09845 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes at least one first contact pin on a first substrate and at least one second contact pin on a second substrate. The at least one first and second contact pins may be included in first and second contact pin arrays. The first and second contact pins of the first and second contact pin arrays may be aligned.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括在第一衬底上的至少一个第一接触引脚和在第二衬底上的至少一个第二接触引脚。 所述至少一个第一和第二接触销可以包括在第一和第二接触针阵列中。 第一和第二接触针阵列的第一和第二接触引脚可以对准。

公开(公告)号：US07775446B2

公开(公告)日：2010-08-17

申请号：US12160541

申请日：2007-02-26

Applicant: Shozo Ochi ,  Osamu Uchida ,  Shigeaki Sakatani ,  Daisuke Sakurai ,  Masato Mori ,  Hiroshi Sakurai ,  Hidenobu Nishikawa

Inventor： Shozo Ochi ,  Osamu Uchida ,  Shigeaki Sakatani ,  Daisuke Sakurai ,  Masato Mori ,  Hiroshi Sakurai ,  Hidenobu Nishikawa

IPC: G06K19/06 ,  H01Q1/00 ,  H01Q1/36

CPC classification number: H01Q1/22 ,  G06K19/07732 ,  G06K19/07749 ,  H01Q7/06 ,  H05K1/0218 ,  H05K1/144 ,  H05K1/148 ,  H05K1/16 ,  H05K2201/043 ,  H05K2201/086 ,  Y10T29/4913

Abstract: Card type information device includes wiring board having a wiring pattern with an electronic component mounted on a first face of wiring board and an antenna connecting electrode, antenna board having antenna pattern with antenna terminal electrode formed on a first face of antenna board, magnetic material placed between wiring board and antenna board confronting each other, flexible wiring board for coupling the antenna connecting electrode to antenna terminal electrode, and housing for accommodating wiring board, antenna board, magnetic material, and flexible wiring board. Wiring board and antenna board are made from one and the same insulating motherboard.

Abstract translation: 卡类型信息装置包括具有安装在布线板的第一面上的电子部件的布线图案和天线连接电极的布线板，天线板天线阵列与天线端子电极形成在天线板的第一面上，磁性材料放置 在布线板和天线板之间，用于将天线连接电极耦合到天线端子电极的柔性布线板和用于容纳布线板，天线板，磁性材料和柔性布线板的壳体。 接线板和天线板由同一个绝缘母板制成。

公开(公告)号：US20090168362A1

公开(公告)日：2009-07-02

申请号：US12317890

申请日：2008-12-30

Applicant: James E. Clayton ,  Zakaryae Fathi

Inventor： James E. Clayton ,  Zakaryae Fathi

IPC: H05K7/20

CPC classification number: H05K1/189 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/07811 ,  H01L2924/15311 ,  H05K1/147 ,  H05K3/0061 ,  H05K2201/043 ,  H05K2201/056 ,  H05K2201/09109 ,  H05K2201/10159 ,  H05K2201/1056 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A multichip module comprises a multilayer substrate circuit having conductive patterns on its surface(s) to which microelectronic device(s) are attached. A part of the substrate is flexible and bifurcated. Two rigid members are attached lengthwise, one on either side of the substrate, and the free ends of the bifurcation are reflexed respectively about these members and bonded to them. Electrodes are located on the bifurcations so that they will be exposed outwardly and/or downwardly after reflexing. The module may further be provided with protective heat spreading covers. The electrodes and rigid members may be configured to engage a mating socket or they may be solderable to a printed circuit board.

Abstract translation: 多芯片模块包括在其表面上具有导电图案的多层衬底电路，微电子器件附接到多个衬底电路。 基板的一部分是柔性的并且分叉。 两个刚性构件纵向连接，一个位于衬底的两侧，并且分叉的自由端分别围绕这些构件反射并结合到它们上。 电极位于分叉处，使得它们在反射之后将向外和/或向下暴露。 模块还可以设置有保护性散热罩。 电极和刚性构件可以被配置为接合配合插座，或者它们可焊接到印刷电路板。

公开(公告)号：US20090011184A1

公开(公告)日：2009-01-08

申请号：US11940900

申请日：2007-11-15

Applicant: YING-LIN CHEN ,  YUNG-CHOU CHEN

Inventor： YING-LIN CHEN ,  YUNG-CHOU CHEN

IPC: B32B3/10 ,  B32B38/04

CPC classification number: H05K3/427 ,  H05K1/0393 ,  H05K1/181 ,  H05K3/4652 ,  H05K2201/0166 ,  H05K2201/043 ,  H05K2201/09536 ,  H05K2203/0264 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T428/24273

Abstract: An exemplary method of making an FPC includes forming a substrate comprising metal foil layers interleaved with intervening layers by: (a) laminating intervening layers with metal foil layers; (b) adhering a covering film to outermost surfaces of the substrate; (c) defining a hole in one side of the substrate through the covering film and at least two metal foil layers and the intervening layer between the at least two metal foil layers by etching or laser technology; and (d) plating a portion of an inner wall of the hole with conductive material to form a via to electrically connect the at least two metal foil layers.

Abstract translation: 制造FPC的示例性方法包括：通过以下步骤形成包含与中间层交错的金属箔层的基板：（a）将介入层与金属箔层层压; （b）将覆盖膜粘附到基板的最外表面; （c）通过蚀刻或激光技术通过覆盖膜和至少两个金属箔层和至少两个金属箔层之间的中间层来限定衬底的一侧中的孔; 以及（d）用导电材料电镀所述孔的内壁的一部分以形成通孔以电连接所述至少两个金属箔层。

公开(公告)号：US07384683B2

公开(公告)日：2008-06-10

申请号：US10571084

申请日：2004-09-10

Applicant: Yoshiaki Echigo ,  Jusirou Eguchi ,  Akira Shigeta ,  Makoto Uchida ,  Shigeru Moteki

Inventor： Yoshiaki Echigo ,  Jusirou Eguchi ,  Akira Shigeta ,  Makoto Uchida ,  Shigeru Moteki

IPC: B32B3/00 ,  H05K1/00 ,  C09J5/10

CPC classification number: H05K1/036 ,  H05K1/0346 ,  H05K1/0393 ,  H05K2201/0195 ,  H05K2201/043 ,  Y10T428/24917 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: The present invention provides a substrate for a flexible printed wiring board including an adhesive layer containing an epoxy resin composition, insulating layers respectively stacked on both sides of the adhesive layer and formed with a pair of films containing a nonthermoplastic polyimide resin, and conductor layers respectively disposed on the outer surfaces of the films. The total thickness of the insulating layers respectively stacked on both sides of the adhesive layer is 10 to 100 μm and 2 to 10 times the thickness of the adhesive layer. The mutual adhesion strength between the insulating layers through the intermediary of the adhesive layer is 7.0 N/cm or more.

Abstract translation: 本发明提供一种柔性印刷电路板用基板，其具有包含环氧树脂组合物的粘合剂层，分别层叠在粘合剂层的两面上的绝缘层，分别形成有一对含有非热塑性聚酰亚胺树脂的膜和导体层 设置在膜的外表面上。 分别层叠在粘合剂层的两面上的绝缘层的总厚度为10〜100μm，粘合剂层的厚度的2〜10倍。 通过粘合剂层中间的绝缘层之间的相互粘附强度为7.0N / cm以上。

公开(公告)号：US07263769B2

公开(公告)日：2007-09-04

申请号：US11252540

申请日：2005-10-19

Applicant: Shinji Morimoto ,  Kouji Nakashima ,  Toyokazu Yoshino ,  Katsuya Okamoto

Inventor： Shinji Morimoto ,  Kouji Nakashima ,  Toyokazu Yoshino ,  Katsuya Okamoto

IPC: H01R3/10

CPC classification number: H05K3/4635 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0221 ,  H05K2201/0379 ,  H05K2201/043 ,  H05K2201/096 ,  H05K2201/10234 ,  H05K2201/10416 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/082 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165

Abstract: A multi-layered flexible print circuit board comprising an insulating layer, a circuit layer formed on the front and back surfaces of the insulating layer and a hole connecting between the circuit layers via the insulating layer, wherein there is provided an electrically-conductive member having a metal layer formed thereon at least on the surface thereof which is press-fitted into the hole to electrically conduct the circuit layer.

Abstract translation: 一种多层柔性印刷电路板，包括绝缘层，形成在绝缘层的前表面和后表面上的电路层和经由绝缘层连接在电路层之间的孔，其中设置有导电构件，其具有 至少在其表面上形成有金属层，该金属层压配合到孔中以导电电路层。

公开(公告)号：US20070035015A1

公开(公告)日：2007-02-15

申请号：US11294842

申请日：2005-12-05

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/34

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/043 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the carriers, at least one dielectric layer formed on the active surface of the semiconductor chip and the surface of the carrier, at least a conductive structure formed in the opening of the dielectric layer, and at least a circuit layer formed on the surface of the dielectric layer wherein the circuit layer is electrically connected to the electrode pad by the conductive structure, so as to form a three-dimensional module to increase the storage capacity dramatically and integrate the semiconductor chips in the carriers for efficiently reducing the size of the module, so that the combinations can be changed flexibly to form the required storage capacity according to the demands.

Abstract translation: 具有嵌入在载体中的半导体芯片的堆叠结构包括两个整体堆叠在一起的载体，至少两个具有活性表面的半导体芯片，电极焊盘和与之对应的非活性表面放置在载体的空腔中，至少一个介电层 半导体芯片的活性表面和载体的表面，至少形成在电介质层的开口中的导电结构，以及至少形成在电介质层的表面上的电路层，其中电路层电连接到 通过导电结构形成三维模块，从而显着提高存储容量，并将半导体芯片集成在载体中，以有效降低模块的尺寸，从而可以灵活更改组合，形成 所需存储容量根据需求。

公开(公告)号：US20060118641A1

公开(公告)日：2006-06-08

申请号：US11176326

申请日：2005-07-08

Applicant: Yi-sung Hwang ,  Sung-dae Cho

Inventor： Yi-sung Hwang ,  Sung-dae Cho

IPC: G06K19/06

CPC classification number: H05K1/117 ,  G06K19/07732 ,  G06K19/07743 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/141 ,  H05K2201/043 ,  H05K2201/09845 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes at least one first contact pin on a first substrate and at least one second contact pin on a second substrate. The at least one first and second contact pins may be included in first and second contact pin arrays. The first and second contact pins of the first and second contact pin arrays may be aligned.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括在第一衬底上的至少一个第一接触引脚和在第二衬底上的至少一个第二接触引脚。 所述至少一个第一和第二接触销可以包括在第一和第二接触针阵列中。 第一和第二接触针阵列的第一和第二接触引脚可以对准。

公开(公告)号：US20050184381A1

公开(公告)日：2005-08-25

申请号：US11060550

申请日：2005-02-18

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC: H01R13/24 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/20 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H01R27/02 ,  H01L23/48 ,  H01R12/00 ,  H01R25/00 ,  H01R31/00 ,  H01R33/88 ,  H01R33/90 ,  H01R33/92 ,  H01R33/94

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A connection member is provided which can be produced without a via-forming step. The connection member 100 includes an insulating substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces; at least one wiring 20 which extends from the upper surface to the lower surface through the side surface.

Abstract translation: 提供了可以在没有通孔形成步骤的情况下制造的连接构件。 连接构件100包括绝缘基板10，其具有上表面10a，与上表面10b相对的下表面10b和连接这些表面的侧表面10c; 至少一个布线20，其通过侧表面从上表面延伸到下表面。

公开(公告)号：US20040264140A1

公开(公告)日：2004-12-30

申请号：US10487895

申请日：2004-02-26

Inventor： Olaf Lucke ,  Bernd Thyzel

IPC: H05K007/20

CPC classification number: H01L23/3735 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/32225 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/0061 ,  H05K2201/043 ,  H05K2203/1572 ,  H01L2924/014

Abstract: The invention relates to a power electronics component that comprises a planar ceramics substrate (2) on whose one face condutor tracks (6), applied in thick-film technique, are disposed for electrically connecting electrical power components (7) of a circuit that are also disposed on the ceramics substrate (2). The ceramics substrate (2), with its other face, is brazed onto a metal support element (1) that serves as a heat spreader. The support element (1) is linked with a thermoconducting housing part (9) of a housing that accommodates the support element (1) in a thermoconductive manner. On the face of the support element (1) facing away from the ceramics substrate (2), approximately opposite the ceramics substrate (2), a second ceramics substrate (4) is brazed onto the ceramics substrate (2) that carries the circuit and has approximately the same dimensions.

Abstract translation: 本发明涉及一种电力电子部件，其包括平面陶瓷基板（2），其平面陶瓷基板（2）的一个面上安置导轨（6）以厚膜技术施加，用于电连接电路的电力部件（7） 也设置在陶瓷基板（2）上。 具有其另一面的陶瓷基板（2）钎焊到用作散热器的金属支撑元件（1）上。 支撑元件（1）与以热传导方式容纳支撑元件（1）的壳体的导热壳体部分（9）连接。 在背离陶瓷基板（2）的支撑元件（1）的表面上，与陶瓷基板（2）大致相反，第二陶瓷基板（4）钎焊到承载电路的陶瓷基板（2）上， 具有大致相同的尺寸。