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    Memory controller and method of operating the memory controller
    61.
    发明授权
    Memory controller and method of operating the memory controller 有权

    公开(公告)号：US11749351B2

    公开(公告)日：2023-09-05

    申请号：US17404652

    申请日：2021-08-17

    Applicant: SK hynix Inc.

    Inventor： Dong Uk Lee ,  Hae Chang Yang ,  Hun Wook Lee

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines.

    Memory device including dynamic programming voltage
    62.
    发明授权
    Memory device including dynamic programming voltage 有权

    公开(公告)号：US11742034B2

    公开(公告)日：2023-08-29

    申请号：US17745415

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Lawrence Celso Miranda

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

    CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

    Voltage generation circuit which is capable of executing high-speed boost operation
    63.
    发明授权
    Voltage generation circuit which is capable of executing high-speed boost operation 有权

    公开(公告)号：US11742033B2

    公开(公告)日：2023-08-29

    申请号：US17647509

    申请日：2022-01-10

    Applicant: Kioxia Corporation

    Inventor： Tatsuro Midorikawa ,  Masami Masuda

    IPC: G11C16/30 ,  H02M3/07

    CPC classification number: G11C16/30 ,  H02M3/07

    Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.

    Adjusting read-level thresholds based on write-to-write delay
    64.
    发明授权
    Adjusting read-level thresholds based on write-to-write delay 有权

    公开(公告)号：US11742029B2

    公开(公告)日：2023-08-29

    申请号：US17402279

    申请日：2021-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

    CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

    Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

    Semiconductor memory device includind boosting circuit that changes generated voltages in write operation
    65.
    发明授权
    Semiconductor memory device includind boosting circuit that changes generated voltages in write operation 有权

    公开(公告)号：US11735277B2

    公开(公告)日：2023-08-22

    申请号：US17470002

    申请日：2021-09-09

    Applicant: Kioxia Corporation

    Inventor： Tomohiko Ito ,  Kazuto Uehara

    IPC: G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459

    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell and a first boosting circuit. The first boosting circuit generates a first voltage, a second voltage, and a third voltage lower than the second voltage at a first output terminal. The first, second and third voltages is used for a write operation. The write operation includes a first program operation and a first verify operation executed after the first program operation. The first boosting circuit generates the first voltage at the first output terminal during the first program operation, generates the third voltage at the first output terminal at end of the first program operation, generates the second voltage at the first output terminal during the first verify operation, and then generates the first voltage to the first output terminal during the first verify operation.

    Dynamic processing of storage command based on internal operations of storage system
    66.
    发明授权
    Dynamic processing of storage command based on internal operations of storage system 有权

    公开(公告)号：US11733868B2

    公开(公告)日：2023-08-22

    申请号：US17382019

    申请日：2021-07-21

    Applicant: Kioxia Corporation

    Inventor： Yaron Klein

    IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C7/04 ,  G11C16/34

    CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G11C7/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3495

    Abstract: Disclosed herein is a device and method for dynamically processing of a command within a storage system. This includes identifying a plurality of non-volatile memory storage locations of the storage system that have at least one operation parameter associated with the plurality of non-volatile memory storage locations. For each identified plurality of non-volatile memory storage locations, there is a determination whether a value of the at least one operation parameter exceeds a predetermined threshold value. That value is representative of operation effects of the storage system on a corresponding storage location of the identified plurality of non-volatile memory storage locations. During operation of the storage system, there is a throttling of execution of the command to access a storage location of the identified plurality of non-volatile memory storage locations that has the value determined to exceed the predetermined threshold value by a throttle amount determined to mitigate an effect of the value exceeding the predetermined threshold value.

    ANALOG PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS
    69.
    发明公开
    ANALOG PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS 审中-公开

    公开(公告)号：US20230253055A1

    公开(公告)日：2023-08-10

    申请号：US18303016

    申请日：2023-04-19

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Jason GUO

    IPC: G11C16/30 ,  G11C16/32

    CPC classification number: G11C16/30 ,  G11C16/32 ,  G11C16/0483

    Abstract: Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

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