公开(公告)号：US20180088804A1

公开(公告)日：2018-03-29

申请号：US15279352

申请日：2016-09-28

申请人： Amazon Technologies, Inc.

发明人： Raviprasad Venkatesha Murthy Mummidi ,  MATTHEW SHAWN WILSON ,  ANTHONY NICHOLAS LIGUORI ,  NAFEA BSHARA ,  Saar Gross ,  Jaspal Kohli

IPC分类号： G06F3/06 ,  G06F12/14 ,  G06F13/20 ,  G06F13/40

CPC分类号： G06F3/061 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0688 ,  G06F12/1408 ,  G06F13/20 ,  G06F13/4004 ,  G06F2212/401 ,  G06F2212/402

摘要： A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

公开(公告)号：US09900267B2

公开(公告)日：2018-02-20

申请号：US15448635

申请日：2017-03-03

申请人： JPMorgan Chase Bank, N.A.

发明人： Philip J. Brandenberger

IPC分类号： H04L12/933 ,  H04L1/00 ,  H04L29/08

CPC分类号： H04L49/15 ,  G06F13/00 ,  G06F13/20 ,  H04L1/0018 ,  H04L12/28 ,  H04L69/324 ,  H04L69/325

摘要： A low latency packet switching system comprising a switching device and a processing device. The switching device may include a first plurality of input/output (I/O) ports and a second plurality of I/O ports, wherein each port of the first plurality of ports may be electrically coupled to a pluggable transceiver socket configured to receive a cable connector. The processing device may include a plurality of transceivers electrically coupled to the second plurality of ports. The switching device may be configured to receive a first electric signal encoding one or more incoming data packets. The switching device may be programmed to output the first electric signal to one or more ports, in accordance with a programmable port mapping scheme. The processing device may be configured to receive the first electric signal and to output a second electric signal encoding one or more modified data packets derived from the incoming data packets.

公开(公告)号：US20180032372A1

公开(公告)日：2018-02-01

申请号：US15219323

申请日：2016-07-26

申请人： International Business Machines Corporation

发明人： Saravanan Devendran ,  Thangadurai Muthusamy

IPC分类号： G06F9/50 ,  G06F9/455 ,  G06F13/20

CPC分类号： G06F9/45558 ,  G06F9/5077 ,  G06F13/20 ,  G06F2009/45579

摘要： A method for reproducing an input/output (I/O) configuration of a computing entity. The method includes a computer processor receiving a request to initiate a first computing entity within a first computing system, where the first computing entity is associated with a first set of I/O configuration information and a first set of I/O resource dictates. The method further includes determining a plurality of I/O resources of the first computing system that are available for allocation and that include a first set of I/O resources that are substantially similar to the first set of I/O resource dictates of the requested first computing entity. The method further includes allocating the first set of I/O resources from the plurality of I/O resources available for allocation. The method further includes provisioning the requested first computing entity within the first computing system based, at least in part, on the allocated first set of I/O resources.

公开(公告)号：US09875196B2

公开(公告)日：2018-01-23

申请号：US14335989

申请日：2014-07-21

申请人： MaxLinear, Inc.

发明人： Timothy Gallagher ,  Glenn DeLucio ,  Curtis Ling

IPC分类号： G06F3/00 ,  G06F13/20 ,  G06F1/32 ,  G06F13/16

CPC分类号： G06F13/20 ,  G06F1/3234 ,  G06F1/3278 ,  G06F13/1673 ,  Y02B70/12 ,  Y02D10/157

摘要： A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of the second MoCA device. The first device may control the power-save operation of the second MoCA device based on an amount of data stored in a buffer, wherein the data stored in the buffer is destined for the second device. The buffer may be in a third device which sends the data to the second device, and/or the buffer may be in the first device. The first device may be operable to buffer data destined for the second device while the second device is in a power-saving state.

公开(公告)号：US20170364477A1

公开(公告)日：2017-12-21

申请号：US15615868

申请日：2017-06-07

申请人： FUJITSU LIMITED

发明人： David Thach ,  Hirotaka TAMURA ,  Sanroku Tsukamoto

IPC分类号： G06F17/11 ,  G06F17/50 ,  G06F7/58 ,  G06F13/20 ,  G06N7/04 ,  G06N7/00

CPC分类号： G06F17/11 ,  G06F7/588 ,  G06F13/20 ,  G06F17/5009 ,  G06N3/0445 ,  G06N3/0472 ,  G06N3/063 ,  G06N5/003 ,  G06N7/005 ,  G06N7/046

摘要： Arithmetic circuits calculate d−1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.

公开(公告)号：US09785626B2

公开(公告)日：2017-10-10

申请号：US15150230

申请日：2016-05-09

申请人： ENPULZ, LLC

发明人： James D. Bennett

IPC分类号： G06F3/041 ,  G06F17/24 ,  G06F3/038 ,  G06F3/048 ,  G06F3/0354 ,  G06F3/0488 ,  G06F3/0489 ,  G06F3/16 ,  G06F13/10 ,  G06F13/20 ,  G06F13/40 ,  G06K9/00 ,  G06K9/18 ,  G10L15/26

CPC分类号： G06F17/242 ,  G06F3/03545 ,  G06F3/038 ,  G06F3/041 ,  G06F3/048 ,  G06F3/04883 ,  G06F3/0489 ,  G06F3/16 ,  G06F13/102 ,  G06F13/20 ,  G06F13/4004 ,  G06F2203/0381 ,  G06K9/00402 ,  G06K9/18 ,  G10L15/26

摘要： A stand alone low cost writing pad includes a rechargeable battery, a low capacity memory, a low power processor, a first pair of connectors and supports audio, video and digital ink capturing functionalities. The writing pad may be detached from and re-attached to a stand alone base unit using the first pair of connectors. The base unit includes another rechargeable battery, high capacity memory, high power processor, and a second pair of connectors. The base unit receives captured audio and digital ink from the writing pad via the communication pathway and the high power processor runs voice recognition and optical character recognition software on received data to generate second data. The second data is displayed on the writing pad and/or stored in the high capacity memory for future use.

公开(公告)号：US09785364B2

公开(公告)日：2017-10-10

申请号：US14886018

申请日：2015-10-17

申请人： International Business Machines Corporation

发明人： Ilias Iliadis ,  Vinodh Venkatesan

IPC分类号： G06F13/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F13/20 ,  G06F13/38 ,  G06F13/16

CPC分类号： G06F3/0619 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/023 ,  G06F12/0623 ,  G06F12/0646 ,  G06F12/0692 ,  G06F13/1694 ,  G06F13/20 ,  G06F13/385 ,  G06F13/387

摘要： A method is provided for increasing data storage reliability in a heterogeneous storage system including multiple storage devices of different types. The devices store respective data subsets of a dataset. The method includes accessing configuration parameters for the dataset including first and second amounts of the data subsets respectively stored on the multiple storage devices. The method further includes estimating an initial global reliability of the heterogeneous storage system for the dataset, based on the configuration parameters. The method also includes determining an increased global reliability of the storage system for the dataset, by estimating a global reliability as would be obtained by modifying at least some of the configuration parameters, whereby at least the first and second amounts of the data subsets respectively stored on the devices are modified. The method further includes reconfiguring the dataset stored across the heterogeneous storage system according to the modified configuration parameters.

公开(公告)号：US09779040B2

公开(公告)日：2017-10-03

申请号：US15064899

申请日：2016-03-09

申请人： FUJITSU LIMITED

发明人： Tomonori Yasumoto

IPC分类号： G06F13/20 ,  G06F13/10 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/20 ,  G06F13/102 ,  G06F13/4068 ,  G06F13/4282

摘要： A portable device includes: a first interface circuit configured to receive, from an information processing apparatus, device information of the information processing apparatus; a second interface circuit configured to receive, from outside device through wireless communication link, a start signal for the information processing apparatus; a memory configured to store a list of information processing apparatuses that are to be permitted to perform wireless communication with the portable device; and a processor configured to compare the device information received from the information processing apparatus with the list stored in the memory, enable wireless communication functionality of the second interface circuit when a result of the comparison indicates that the portable device is coupled to an information processing apparatus which is permitted to perform wireless communication, and transmit a start signal to the information processing apparatus when the start signal is received by using the enabled wireless communication functionality.

公开(公告)号：US20170262388A1

公开(公告)日：2017-09-14

申请号：US15446558

申请日：2017-03-01

申请人： MITAC COMPUTING TECHNOLOGY CORPORATION

发明人： Chi-Jung LIN ,  Chi-Hao KUAN ,  Hsiang-Jui HUANG

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/20

CPC分类号： G06F13/1668 ,  G06F13/20 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

摘要： A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.

公开(公告)号：US20170249272A1

公开(公告)日：2017-08-31

申请号：US15460844

申请日：2017-03-16

申请人： Bedrock Automation Platforms Inc.

发明人： James G. Calvin ,  Albert Rooyakkers

IPC分类号： G06F13/40 ,  G06F13/20 ,  G06F13/364 ,  G06F13/42 ,  G06F15/173 ,  G06F15/16

CPC分类号： G06F13/4022 ,  G06F13/20 ,  G06F13/364 ,  G06F13/4282 ,  G06F15/16 ,  G06F15/17312 ,  G06F2213/0004 ,  G06F2213/0022 ,  G06F2213/0024

摘要： A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.