公开(公告)号：US09354907B1

公开(公告)日：2016-05-31

申请号：US13661258

申请日：2012-10-26

Applicant: Symantec Corporation

Inventor： Ravindra V. Teli ,  Mohammed Eliyas N. A. Shaikh ,  Chirag Dalal

IPC: G06F12/00 ,  G06F9/455 ,  G06F12/10

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45575

Abstract: Various systems and methods for restoring a virtual machine and virtual machine data. For example, one method can involve receiving a request to restore the virtual machine and virtual machine data. The virtual machine data can include part or all of a virtual disk associated with the virtual machine. Both the virtual machine and the virtual machine data are stored in one or more backup storage devices. In response to the request, the virtual machine is restored from the backup storage device to a local storage device, and restoration of the virtual machine data is initiated. While the virtual machine data is being migrated from backup to local storage, I/O requests are received and processed. Processing the I/O request can involve performing the I/O requests to both the backup storage device and the local storage device.

Abstract translation: 用于恢复虚拟机和虚拟机数据的各种系统和方法。 例如，一种方法可以涉及接收恢复虚拟机和虚拟机数据的请求。 虚拟机数据可以包括与虚拟机相关联的虚拟磁盘的部分或全部。 虚拟机和虚拟机数据都存储在一个或多个备份存储设备中。 响应该请求，将虚拟机从备份存储设备恢复到本地存储设备，并启动虚拟机数据的恢复。 当虚拟机数据从备份迁移到本地存储时，I / O请求被接收和处理。 处理I / O请求可能涉及对备份存储设备和本地存储设备执行I / O请求。

公开(公告)号：US09330023B2

公开(公告)日：2016-05-03

申请号：US14297326

申请日：2014-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Bybell ,  Bradly G. Frey ,  Michael K. Gschwind ,  Benjamin Herrenschmidt ,  Paul Mackerras

IPC: G06F12/10 ,  G06F12/14

CPC classification number: G06F12/1045 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/684

Abstract: For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space.

Abstract translation: 对于请求访问特定地址的处理器的控制中的当前上下文，翻译后备缓冲器（TLB）控制器指定具有指示当前上下文的特权设置的逻辑分区标识符值的虚拟地址，指示是否 地址在共享地址空间内，以及包括特定地址的至少一部分的有效地址。 响应于虚拟地址不匹配TLB内的至少一个条目，包括为至少一个先前地址的至少一个先前转换而存储的至少一个条目，TLB控制器使用至少一个 页面表，并且使用虚拟地址和实际页面号码向TLB添加新条目，其中TLB内的每个至少一个条目从多个特权设置中识别单独的权限设置，以及单独的指示符是否是地址是 在共享地址空间内。

公开(公告)号：US09317445B2

公开(公告)日：2016-04-19

申请号：US13764602

申请日：2013-02-11

Applicant: Spansion LLC

Inventor： Frank Edelhaeuser ,  Clifford A Zitlaw ,  Jeremy Mah

IPC: G06F12/06 ,  G06F12/10 ,  G06F12/02 ,  G06F12/08 ,  G11C7/22 ,  G06F9/38

CPC classification number: G06F12/0653 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F9/3802 ,  G06F11/1068 ,  G06F12/02 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/10 ,  G06F12/1036 ,  G06F2212/1041 ,  G06F2212/657 ,  G11C7/22 ,  G11C29/52 ,  G11C2207/2245

Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.

公开(公告)号：US09298639B2

公开(公告)日：2016-03-29

申请号：US14755355

申请日：2015-06-30

Applicant: Intel Corporation

Inventor： Baohong Liu ,  Ritu Sood ,  Kuo-Lang Tseng ,  Madhukar Tallam

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/14 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/145 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/657

Abstract: Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit. The virtualization unit is to transfer control of the processor to a virtual machine. The memory management unit is to perform, in response to an attempt to execute on the virtual machine an instruction stored on a first page, a page walk through a paging structure to find a second page and to allow access to the second page without exiting the virtual machine based at least in part on a bit being set in a leaf level entry corresponding to the second page in the paging structure and a corresponding bit being set in each entry corresponding to the first page in each level of the paging structure.

公开(公告)号：US20160085687A1

公开(公告)日：2016-03-24

申请号：US14490902

申请日：2014-09-19

Applicant: NIR BARUCH ,  NIR ATZMON ,  DAVID W. TODD

Inventor： NIR BARUCH ,  NIR ATZMON ,  DAVID W. TODD

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1441 ,  G06F2212/657

Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Abstract translation: 布置成接收存储器访问事务并提供其存储器管理功能的存储器管理组件，以及在处理系统内提供存储器管理功能的方法。 存储器管理组件包括第一存储器管理模块，其被布置为根据寻呼存储器管理方案为接收到的存储器访问事务提供存储器管理功能，以及至少一个另外的存储器管理模块，被配置为提供用于存储器访问事务的存储器管理功能 根据地址范围内存管理方案。

公开(公告)号：US09286235B2

公开(公告)日：2016-03-15

申请号：US13538900

申请日：2012-06-29

Applicant: Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Uday Savagaonkar ,  Francis Mckeen ,  Carlos Rozas ,  Michael Goldsmith ,  Prashant Dewan

Inventor： Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Uday Savagaonkar ,  Francis Mckeen ,  Carlos Rozas ,  Michael Goldsmith ,  Prashant Dewan

IPC: G06F9/26 ,  G06F9/34 ,  G06F12/10

CPC classification number: G06F12/109 ,  G06F12/0284 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

Abstract translation: 公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。 在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。 存储器接口是使用物理内存地址访问系统内存。 地址转换硬件是支持将虚拟内存地址转换为物理内存地址。 虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。 虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

公开(公告)号：US09280488B2

公开(公告)日：2016-03-08

申请号：US13646770

申请日：2012-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Bybell ,  David D. Dukro ,  Bradly G. Frey ,  Michael K. Gschwind

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1036 ,  G06F2212/151

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract translation: 提供了一种地址转换能力，其中使用不同类型的翻译结构将存储器地址从一种格式转换为另一格式。 在系统配置中同时支持多种翻译结构格式（例如，多页表格式，例如散列页表和分层页表）。 这有助于在虚拟操作系统中提供访客访问，和/或翻译格式的混合以更好地匹配被翻译的数据访问模式。

公开(公告)号：US09268694B2

公开(公告)日：2016-02-23

申请号：US14038225

申请日：2013-09-26

Applicant: Cavium, Inc.

Inventor： Wilson P. Snyder, II ,  Bryan W. Chin ,  Shubhendu S. Mukherjee ,  Michael Bertone ,  Richard E. Kessler

IPC: G06F13/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F2212/151 ,  G06F2212/681

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.

Abstract translation: 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 此外，折叠TLB是从MTLB导出的附加高速缓存存储折叠的折叠。 MTLB中的条目，折叠的TLB和其他高速缓存可以保持一致。

公开(公告)号：US20160041922A1

公开(公告)日：2016-02-11

申请号：US14761126

申请日：2014-11-26

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： TERRY PARKS ,  COLIN EDDY ,  VISWANATH MOHAN ,  JOHN D. BUNDA

IPC: G06F12/10 ,  G06F15/78

CPC classification number: G06F12/0891 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1063 ,  G06F12/109 ,  G06F15/7839 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/683

Abstract: A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.

Abstract translation: 处理器包括翻译后备缓冲器（TLB）和映射模块。 TLB包括多个条目，其中多个条目的每个条目被配置为保存地址转换和有效位向量，其中，对于相应的地址转换上下文，有效位向量的每个比特指示地址转换是 如果设置有效，如果清除则为无效。 TLB还包括具有对应于多个条目的有效位向量的比特的无效比特向量，其中无效比特向量的设置比特指示同时清除每个条目的有效比特向量的相应比特 多个条目。 映射模块生成无效位向量。

公开(公告)号：US09256550B2

公开(公告)日：2016-02-09

申请号：US13432381

申请日：2012-03-28

Applicant: Anthony J. Bybell ,  Michael K. Gschwind

Inventor： Anthony J. Bybell ,  Michael K. Gschwind

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1027 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/684

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.