公开(公告)号：US20130040445A1

公开(公告)日：2013-02-14

申请号：US13583564

申请日：2011-11-07

Applicant: Ryosuke Kubota ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

Inventor： Ryosuke Kubota ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

IPC: H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/268 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.

Abstract translation: 制备具有表面的碳化硅衬底。 通过从表面注入离子到碳化硅衬底中形成杂质区。 执行用于激活杂质区域的退火。 退火包括将具有第一波长的第一激光施加到碳化硅衬底的表面的步骤，以及将具有第二波长的第二激光施加到碳化硅衬底的表面的步骤。 碳化硅衬底分别在第一和第二波长处具有第一和第二消光系数。 第一消光系数与第一波长的比率高于5×10 5 / m。 第二消光系数与第二波长的比率低于5×10 5 / m。 因此，可以减少在激光退火期间对碳化硅衬底的表面的损坏。

公开(公告)号：US20120286291A1

公开(公告)日：2012-11-15

申请号：US13520702

申请日：2011-03-04

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L29/161 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/94

Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

Abstract translation: 提供一种具有优异的包括沟道迁移率的电特性的碳化硅半导体器件及其制造方法。 制造碳化硅半导体器件的方法包括：制备碳化硅半导体膜的外延层形成步骤; 在所述半导体膜的表面上形成氧化膜的栅极绝缘膜形成工序; 在含氮气氛中对形成有氧化膜的半导体膜进行热处理的氮退火工序; 以及后处理工序，在氮退火工序后，在含有惰性气体的气氛中对形成有氧化膜的半导体膜进行后热处理。 后热处理工序中的热处理温度高于氮退火工序中的热处理温度，低于氧化膜的熔点。

公开(公告)号：US20120248462A1

公开(公告)日：2012-10-04

申请号：US13435863

申请日：2012-03-30

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

Abstract: An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.

Abstract translation: IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为 相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触 在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

公开(公告)号：US20120018743A1

公开(公告)日：2012-01-26

申请号：US13190001

申请日：2011-07-25

Applicant: Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

Inventor： Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

IPC: H01L29/772

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

Abstract: A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×1016 cm−3.

Abstract translation: MOSFET包括碳化硅衬底，其包括相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面，形成在主表面上的缓冲层和漂移层， 形成在漂移层上并与漂移层接触的栅氧化膜，以及在漂移层中形成的ap导电型的p型体区域，以包括与栅氧化膜接触的区域。 p型体区的p型杂质密度为5×1016cm-3以上。

公开(公告)号：US20110241022A1

公开(公告)日：2011-10-06

申请号：US13133284

申请日：2009-12-09

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L29/12 ,  H01L21/28

CPC classification number: G01V8/12 ,  H01L21/02021

Abstract: A substrate, the presence of which can be detected with a method similar to a conventional method of detecting a Si substrate even if the substrate is transparent, and a method of manufacturing the substrate are provided. Light incident on an end portion of a transparent substrate is not transmitted through the substrate as with the light incident on a central portion of the substrate, but is totally reflected from a total reflection surface in a detection region present in at least a portion of the end portion of the substrate. A photoelectric sensor can recognize that a ratio of transmission of the light at the end portion of the substrate has become smaller, thereby detecting the presence of the substrate.

Abstract translation: 基板，即使基板是透明的，也可以利用与传统的检测Si基板的方法类似的方法检测其存在，以及制造基板的方法。 入射到透明基板的端部的光不像入射在基板的中心部分的光那样透过基板，而是在存在于基板的至少一部分中的检测区域中的全反射面全反射 基底的端部。 光电传感器能够识别出基板端部的光的透过率变小，从而检测出基板的存在。

公开(公告)号：US20100314626A1

公开(公告)日：2010-12-16

申请号：US12515386

申请日：2007-11-16

Applicant: Shin Harada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Takeyoshi Masuda

IPC: H01L29/24 ,  H01L21/20

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02639 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. An extended terrace surface is formed at a surface of an initial growth layer on a 4H—SiC substrate by annealing with the initial growth layer covered with an Si film, and then a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion having a polytype stable at a low temperature is grown on the extended terrace surface, and a 4H—SiC portion is grown on the other region. A trench is formed by selectively removing the 3C—SiC portion with the 4H—SiC portion remaining, and a gate electrode of a UMOSFET is formed in the trench. A channel region of the UMOSFET can be controlled to have a low-order surface, and a silicon carbide semiconductor device having high channel mobility and excellent performance characteristics is obtained.

Abstract translation: 获得具有优异性能的碳化硅半导体器件及其制造方法。 通过用覆盖有Si膜的初始生长层退火，在4H-SiC衬底上的初始生长层的表面上形成延伸的台面表面，然后在初始生长层上外延生长新的生长层。 在延伸的台面上生长具有低温稳定性的3C-SiC部分，在其他区域生长4H-SiC部分。 通过选择性地除去具有4H-SiC部分的3C-SiC部分形成沟槽，并且在沟槽中形成UMOSFET的栅电极。 可以将UMOSFET的沟道区域控制为具有低阶表面，并且获得具有高沟道迁移率和优异性能特性的碳化硅半导体器件。

公开(公告)号：US20100221917A1

公开(公告)日：2010-09-02

申请号：US12161832

申请日：2006-12-06

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L21/04

CPC classification number: H01L29/7802 ,  H01J37/3244 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/049 ,  H01L21/3147 ,  H01L21/3148 ,  H01L21/31658 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068

Abstract: A method of manufacturing a silicon carbide semiconductor device having low interface state density in an interface region between a gate insulating film and a silicon carbide layer is provided. An epitaxially grown layer is grown on a 4H-SiC substrate, and thereafter ion implantation is performed to form a p well region, a source region and a p+ contact region that are ion implantation layers. Thereafter, using thermal oxidation or CVD, the gate insulating film formed by a silicon oxide film is formed on the p well region, the source region and the p+ contact region. Then, plasma is generated using a gas containing N2O, which is the gas containing at least any one of oxygen and nitrogen, so as to expose the gate insulating film to plasma.

Abstract translation: 提供了在栅极绝缘膜和碳化硅层之间的界面区域中制造具有低界面态密度的碳化硅半导体器件的方法。 在4H-SiC衬底上生长外延生长层，然后进行离子注入以形成作为离子注入层的p阱区，源极区和p +接触区。 此后，使用热氧化或CVD，在p阱区域，源极区域和p +接触区域上形成由氧化硅膜形成的栅极绝缘膜。 然后，使用含有N 2 O的气体产生等离子体，N 2 O是含有氧和氮中的至少一种的气体，以便将栅极绝缘膜暴露于等离子体。

公开(公告)号：US09070567B2

公开(公告)日：2015-06-30

申请号：US13128438

申请日：2010-02-09

Applicant: Makoto Sasaki ,  Takeyoshi Masuda

Inventor： Makoto Sasaki ,  Takeyoshi Masuda

IPC: C30B21/02 ,  H01L29/06 ,  C30B29/36 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L23/544 ,  H01L29/16

CPC classification number: H01L29/7802 ,  C30B29/36 ,  H01L23/544 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10T83/04 ,  H01L2924/00

Abstract: A SiC substrate includes a first orientation flat parallel to the direction, and a second orientation flat being in a direction intersecting the first orientation flat and being different from the first orientation flat in length. An alternative SiC substrate has a rectangular plane shape, and a main surface of the substrate includes a first side parallel to the direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side. A length of the third side projected in a direction in which the first side extends is different from a length of the third side projected in a direction in which the second side extends.

Abstract translation: SiC衬底包括平行于<11-20>方向的第一取向平板和与第一取向平面相交的方向并且与第一取向平面不同的第二取向平面。 替代的SiC衬底具有矩形平面形状，并且衬底的主表面包括平行于<11-20>方向的第一侧，在垂直于第一侧的方向上的第二侧和连接第一侧的第三侧 一边到第二边 沿第一侧延伸的方向突出的第三侧的长度不同于沿第二侧延伸的方向突出的第三侧的长度。

公开(公告)号：US09006745B2

公开(公告)日：2015-04-14

申请号：US13522216

申请日：2011-10-25

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/66 ,  H01L21/332 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/66734 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract translation: MOSFET包括碳化硅衬底，有源层，栅氧化物膜和栅电极。 有源层包括通过向栅电极施加电压而在与栅极氧化膜接触的区域处形成反型层的主体区域。 身体区域包括布置在反型层形成区域的低浓度区域，并且在反转层中包含低浓度杂质和与反转层中的载流子移动方向上的低浓度区域相邻的高浓度区域 形成反型层的区域，并且含有浓度高于低浓度区域的杂质。

公开(公告)号：US08772139B2

公开(公告)日：2014-07-08

申请号：US13577836

申请日：2011-12-07

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/7802 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.

Abstract translation: 制造MOSFET的方法包括以下步骤：制备碳化硅衬底，在碳化硅衬底上形成有源层，在有源层上形成栅极氧化膜，在栅极氧化膜上形成栅电极，形成源极接触 电极，并且在源极接触电极上形成源极互连。 形成源极互连的步骤包括在源极接触电极上形成导体膜并通过用反应离子蚀刻蚀刻导体膜来处理导体膜的步骤。 然后，制造MOSFET的方法还包括在处理导体膜的步骤之后执行将碳化硅衬底加热到​​不低于50℃的温度的退火的步骤。