公开(公告)号：US20230352071A1

公开(公告)日：2023-11-02

申请号：US18169560

申请日：2023-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Lee ,  Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659

Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of memory cells, a first reference cell connected to a first subset of the plurality of memory cells via a first common source line, and a second reference cell connected to a second subset of the plurality of memory storage cells via a second common source line. The semiconductor device also includes a sense amplifier configured to, when reading from a first memory cell of the first subset, receive an output from the second reference cell and an output from the first memory cell.

公开(公告)号：US11735238B2

公开(公告)日：2023-08-22

申请号：US17855107

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-An Lai ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C7/22 ,  G11C7/10 ,  G11C13/00 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/14 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

公开(公告)号：US20230260559A1

公开(公告)日：2023-08-17

申请号：US18138305

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C7/20 ,  G06F11/14 ,  G11C11/4072 ,  G06F11/30 ,  G06F1/30 ,  G11C5/14

CPC classification number: G11C7/20 ,  G06F11/1469 ,  G11C11/4072 ,  G06F11/3058 ,  G06F1/30 ,  G06F11/3037 ,  G11C5/148

Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

公开(公告)号：US11720130B2

公开(公告)日：2023-08-08

申请号：US17397542

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-An Chang ,  Chieh-Pu Lo ,  Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G05F1/575 ,  G11C11/16

CPC classification number: G05F1/575 ,  G11C11/1697

Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.

公开(公告)号：US11693560B2

公开(公告)日：2023-07-04

申请号：US17155362

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chi-Fu Lee ,  Jonathan Tsung-Yung Chang

IPC: G06F3/06 ,  G11C11/419 ,  G06F7/544

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673 ,  G06F7/5443 ,  G11C11/419

Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

公开(公告)号：US20230065104A1

公开(公告)日：2023-03-02

申请号：US17981977

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Pei-Ling Tseng

IPC: G11C13/00

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

公开(公告)号：US20220360254A1

公开(公告)日：2022-11-10

申请号：US17815322

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: H03K3/356

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

公开(公告)号：US20220319558A1

公开(公告)日：2022-10-06

申请号：US17843786

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/06

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US11450364B2

公开(公告)日：2022-09-20

申请号：US17337889

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

IPC: G11C7/12 ,  G11C7/10 ,  G11C5/06 ,  G11C16/04 ,  G11C16/30

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

公开(公告)号：US20220293141A1

公开(公告)日：2022-09-15

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.