Semiconductor device with reduced loading effect

    公开(公告)号:US11264281B2

    公开(公告)日:2022-03-01

    申请号:US16924686

    申请日:2020-07-09

    摘要: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

    Method and equipment for forming gaps in a material layer

    公开(公告)号:US11244856B2

    公开(公告)日:2022-02-08

    申请号:US15843185

    申请日:2017-12-15

    摘要: A method and equipment for forming gaps in a material layer are provided. The equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. In the method for forming gaps in a material layer, at first, the semiconductor device is provided. Then, a material layer of the semiconductor device is etched to form vertical gaps in the material layer. Thereafter, the vertical sidewall of each of the vertical gaps is etched in accordance with a predetermined gap profile by using directional charged particle beams. The directional charged particle beams are provided by the etching device, and each of the directional charged particle beams has two energy peaks.

    SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

    公开(公告)号:US20220020644A1

    公开(公告)日:2022-01-20

    申请号:US17143698

    申请日:2021-01-07

    IPC分类号: H01L21/8234 H01L21/3065

    摘要: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The process of performing the oxygen-free cyclic etching process can include performing a first etching process to selectively etch the dielectric layer over the channel layer of the second portion of the fin structure with a first etching selectivity, and performing a second etching process to selectively etch the dielectric layer over the channel layer of the second portion of fin structure with a second etching selectivity greater than the first etching selectivity

    Air gap spacer and related methods
    66.
    发明授权

    公开(公告)号:US11205700B2

    公开(公告)日:2021-12-21

    申请号:US16504117

    申请日:2019-07-05

    摘要: A method of forming an air-gap spacer in a semiconductor device includes providing a device including a gate stack, a plurality of spacer layers disposed on a sidewall of the gate stack, and a source/drain feature adjacent to the gate stack. In some embodiments, a first spacer layer of the plurality of spacer layers is removed to form an air gap on the sidewall of the gate stack. In various examples, a first sealing layer is then deposited over a top portion of the air gap to form a sealed air gap, and a second sealing layer is deposited over the first sealing layer. Thereafter, a first self-aligned contact (SAC) layer is etched from over the source/drain feature using a first etching process. In various embodiments, the first etching process selectively etches the first SAC layer while the first and second sealing layers remain unetched.

    Semiconductor Device and Method of Manufacture

    公开(公告)号:US20210111071A1

    公开(公告)日:2021-04-15

    申请号:US17113836

    申请日:2020-12-07

    摘要: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.