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公开(公告)号:US20220130693A1
公开(公告)日:2022-04-28
申请号:US17572162
申请日:2022-01-10
发明人: Han-Yu Lin , Yi-Ruei Jhan , Fang-Wei Lee , Li-Te Lin , Pinyen Lin , Tze-Chung Lin
IPC分类号: H01L21/67 , H01L21/677 , C23C16/452
摘要: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.
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公开(公告)号:US11264281B2
公开(公告)日:2022-03-01
申请号:US16924686
申请日:2020-07-09
发明人: Wei-Lun Chen , Li-Te Lin , Chao-Hsien Huang
IPC分类号: H01L21/8234 , H01L27/088 , H01L29/06 , H01L21/3065 , H01L21/308 , H01L29/10
摘要: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
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公开(公告)号:US11244856B2
公开(公告)日:2022-02-08
申请号:US15843185
申请日:2017-12-15
发明人: Chan-Syun David Yang , Li-Te Lin , Yu-Ming Lin
IPC分类号: H01L21/311 , H01L21/768 , H01L21/67 , H01L21/683
摘要: A method and equipment for forming gaps in a material layer are provided. The equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. In the method for forming gaps in a material layer, at first, the semiconductor device is provided. Then, a material layer of the semiconductor device is etched to form vertical gaps in the material layer. Thereafter, the vertical sidewall of each of the vertical gaps is etched in accordance with a predetermined gap profile by using directional charged particle beams. The directional charged particle beams are provided by the etching device, and each of the directional charged particle beams has two energy peaks.
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公开(公告)号:US20220020644A1
公开(公告)日:2022-01-20
申请号:US17143698
申请日:2021-01-07
发明人: Han-Yu LIN , Jhih-Rong Huang , Yen-Tien Tung , Tzer-Min Shen , Fu-Ting Yen , Gary Chan , Keng-Chu Lin , Li-Te Lin , Pinyen Lin
IPC分类号: H01L21/8234 , H01L21/3065
摘要: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The process of performing the oxygen-free cyclic etching process can include performing a first etching process to selectively etch the dielectric layer over the channel layer of the second portion of the fin structure with a first etching selectivity, and performing a second etching process to selectively etch the dielectric layer over the channel layer of the second portion of fin structure with a second etching selectivity greater than the first etching selectivity
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公开(公告)号:US11222794B2
公开(公告)日:2022-01-11
申请号:US16044314
申请日:2018-07-24
发明人: Han-Yu Lin , Yi-Ruei Jhan , Fang-Wei Lee , Li-Te Lin , Pinyen Lin , Tze-Chung Lin
IPC分类号: H01L21/67 , H01L21/677 , C23C16/452
摘要: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.
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公开(公告)号:US11205700B2
公开(公告)日:2021-12-21
申请号:US16504117
申请日:2019-07-05
发明人: Chan Syun David Yang , Li-Te Lin
IPC分类号: H01L29/10 , H01L29/66 , H01L21/3065 , H01L29/78
摘要: A method of forming an air-gap spacer in a semiconductor device includes providing a device including a gate stack, a plurality of spacer layers disposed on a sidewall of the gate stack, and a source/drain feature adjacent to the gate stack. In some embodiments, a first spacer layer of the plurality of spacer layers is removed to form an air gap on the sidewall of the gate stack. In various examples, a first sealing layer is then deposited over a top portion of the air gap to form a sealed air gap, and a second sealing layer is deposited over the first sealing layer. Thereafter, a first self-aligned contact (SAC) layer is etched from over the source/drain feature using a first etching process. In various embodiments, the first etching process selectively etches the first SAC layer while the first and second sealing layers remain unetched.
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公开(公告)号:US11201243B2
公开(公告)日:2021-12-14
申请号:US16559343
申请日:2019-09-03
发明人: Chansyun David Yang , Han-Yu Lin , Chun-Yu Chen , Chih-Ching Wang , Fang-Wei Lee , Tze-Chung Lin , Li-Te Lin , Gwan-Sin Chang , Pinyen Lin
IPC分类号: H01L29/78 , H01L21/8234 , H01L29/66 , H01L29/417 , H01L29/06
摘要: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
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公开(公告)号:US20210327764A1
公开(公告)日:2021-10-21
申请号:US17362025
申请日:2021-06-29
发明人: Han-Yu Lin , Yi-Ruei Jhan , Fang-Wei Lee , Tze-Chung Lin , Chao-Hsien Huang , Li-Te Lin , Pinyen Lin , Akira Mineji
IPC分类号: H01L21/8234 , H01L27/088 , H01L21/265 , H01L21/764 , H01L21/3105 , H01L21/02 , H01L21/311
摘要: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.
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公开(公告)号:US11024721B2
公开(公告)日:2021-06-01
申请号:US16559369
申请日:2019-09-03
发明人: Zhi-Qiang Wu , Kuo-An Liu , Chan-Lon Yang , Bharath Kumar Pulicherla , Li-Te Lin , Chung-Cheng Wu , Gwan-Sin Chang , Pinyen Lin
IPC分类号: H01L21/311 , H01L29/66 , H01L21/3213 , H01L29/78 , H01L29/49 , H01L29/40
摘要: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.
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公开(公告)号:US20210111071A1
公开(公告)日:2021-04-15
申请号:US17113836
申请日:2020-12-07
发明人: Chan Syun David Yang , Li-Te Lin , Chun-Jui Huang
IPC分类号: H01L21/768 , H01L29/66 , H01L23/535 , H01L29/78 , H01L29/417
摘要: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
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