- 专利标题: Semiconductor device with reduced loading effect
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申请号: US16924686申请日: 2020-07-09
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公开(公告)号: US11264281B2公开(公告)日: 2022-03-01
- 发明人: Wei-Lun Chen , Li-Te Lin , Chao-Hsien Huang
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L21/3065 ; H01L21/308 ; H01L29/10
摘要:
The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
公开/授权文献
- US20220013411A1 SEMICONDUCTOR DEVICE WITH REDUCED LOADING EFFECT 公开/授权日:2022-01-13
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