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    Integration of Magneto-Resistive Random Access Memory and Capacitor
    62.
    发明申请
    Integration of Magneto-Resistive Random Access Memory and Capacitor 审中-公开
    磁阻随机存取存储器和电容器的集成

    公开(公告)号：US20140264463A1

    公开(公告)日：2014-09-18

    申请号：US14066978

    申请日：2013-10-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chung-Cheng Chou ,  Ya-Chen Kao ,  Tien-Wei Chiang

    IPC: H01L27/22 ,  H01L43/12

    CPC classification number: H01L27/228 ,  H01L43/10 ,  H01L43/12

    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

    Abstract translation: 本公开提供了半导体结构的一个实施例，其包括形成在半导体衬底上的第一金属层，其中第一金属层包括第一区域中的第一金属特征和第二区域中的第二金属特征; 设置在所述第一金属层上的第二金属层，其中所述第二金属层包括所述第一区域中的第三金属特征和在第二区域中的第四金属特征; 夹在所述第一金属特征和所述第三金属特征之间的磁阻存储器件; 以及夹在第二金属特征和第四金属特征之间的电容器。

    Memory cell array circuit and method of forming the same
    64.
    发明授权
    Memory cell array circuit and method of forming the same 有权

    公开(公告)号：US12230323B2

    公开(公告)日：2025-02-18

    申请号：US18304297

    申请日：2023-04-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

    IPC: G11C13/00

    Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

    VOLTAGE REGULATORS WITH SHARED DECOUPLING CAPACITOR FOR MEMORY DEVICES
    65.
    发明申请
    VOLTAGE REGULATORS WITH SHARED DECOUPLING CAPACITOR FOR MEMORY DEVICES 有权

    公开(公告)号：US20240411334A1

    公开(公告)日：2024-12-12

    申请号：US18331620

    申请日：2023-06-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Zheng-Jun Lin ,  Chen-Ming Hung ,  Chung-Cheng Chou

    IPC: G05F1/59 ,  G11C11/16 ,  G11C13/00

    Abstract: A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.

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