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    Dual row-column major dram
    62.
    发明授权
    Dual row-column major dram 有权

    公开(公告)号：US11568920B2

    公开(公告)日：2023-01-31

    申请号：US15713587

    申请日：2017-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F3/00 ,  G11C11/408 ,  G06F3/06 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/4076 ,  G11C7/10 ,  G11C5/04

    Abstract: A memory device includes an array of 2T1C DRAM cells and a memory controller. The DRAM cells are arranged as a plurality of rows and columns of DRAM cells. The memory controller is internal to the memory device and is coupled to the array of DRAM cells. The memory controller is capable of receiving commands input to the memory device and is responsive to the received commands to control row-major access and column-major access to the array of DRAM cells. In one embodiment, each transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor. In another embodiment, a first transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor, and a second transistor of the 2T1C memory cell includes a gate terminal directly coupled to the storage node of the capacitor.

    Bandwidth boosted stacked memory
    64.
    发明授权
    Bandwidth boosted stacked memory 有权

    公开(公告)号：US11513965B2

    公开(公告)日：2022-11-29

    申请号：US17156362

    申请日：2021-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G06F12/0879 ,  G11C11/417

    Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

    Systems and methods for write and flush support in hybrid memory
    65.
    发明授权
    Systems and methods for write and flush support in hybrid memory 有权

    公开(公告)号：US11175853B2

    公开(公告)日：2021-11-16

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/00 ,  G06F12/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/02

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

    Coordinated near-far memory controller for process-in-HBM
    68.
    发明授权
    Coordinated near-far memory controller for process-in-HBM 有权

    公开(公告)号：US10437482B2

    公开(公告)日：2019-10-08

    申请号：US15723014

    申请日：2017-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A method of coordinating memory commands in a high-bandwidth memory HBM+ system, the method including sending a host memory controller command from a host memory controller to a memory, receiving the host memory controller command at a coordinating memory controller, forwarding the host memory controller command from the coordinating memory controller to the memory, and scheduling, by the coordinating memory controller, a coordinating memory controller command based on the host memory controller command.

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    69.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 审中-公开

    公开(公告)号：US20190179705A1

    公开(公告)日：2019-06-13

    申请号：US16276369

    申请日：2019-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C5/04

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

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