公开(公告)号：US11994948B2

公开(公告)日：2024-05-28

申请号：US18164349

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C29/70

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US10977118B2

公开(公告)日：2021-04-13

申请号：US16276304

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US10705908B2

公开(公告)日：2020-07-07

申请号：US16015534

申请日：2018-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US09251863B2

公开(公告)日：2016-02-02

申请号：US14268675

申请日：2014-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Joong Kim ,  Dongyang Lee

IPC: G11C7/00 ,  G11C5/06 ,  H01L25/065

CPC classification number: G11C5/063 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.

Abstract translation: 公开了一种半导体存储器件，其包括安装在封装内的多个通道存储器，并且能够最小化或减少硅通孔的数量。 利用半导体存储器件，通过共享总线施加两个或更多个通道上的行命令或行地址。 半导体存储器件能够通过减少硅通孔的数量来减少管芯​​尺寸的开销。 还提供了使用共享总线驱动包括多个存储器的多通道半导体存储器件的方法。

公开(公告)号：US20140241024A1

公开(公告)日：2014-08-28

申请号：US14268675

申请日：2014-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Joong Kim ,  Dongyang Lee

IPC: G11C5/06

CPC classification number: G11C5/063 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.

Abstract translation: 公开了一种半导体存储器件，其包括安装在封装内的多个通道存储器，并且能够最小化或减少硅通孔的数量。 利用半导体存储器件，通过共享总线施加两个或更多个通道上的行命令或行地址。 半导体存储器件能够通过减少硅通孔的数量来减少管芯​​尺寸的开销。 还提供了使用共享总线驱动包括多个存储器的多通道半导体存储器件的方法。

公开(公告)号：US11818423B2

公开(公告)日：2023-11-14

申请号：US16918385

申请日：2020-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Man Lee ,  Mi-Sun Kim ,  Sang-Hun Kim ,  Hyun-Joong Kim ,  Mi-Ra Seo ,  Woo-Cheol Jung ,  Yong-Gu Lee

IPC: H04N21/439 ,  H04N21/4788 ,  H04N21/4363 ,  H04N21/61 ,  H04N21/81 ,  H04L65/00 ,  H04L65/1083 ,  H04L65/401 ,  H04L65/1089 ,  G06F3/16 ,  H04N21/41

CPC classification number: H04N21/4394 ,  G06F3/16 ,  G06F3/165 ,  H04L65/00 ,  H04L65/1083 ,  H04L65/1089 ,  H04L65/4015 ,  H04N21/41265 ,  H04N21/43637 ,  H04N21/4788 ,  H04N21/6131 ,  H04N21/8106

Abstract: A method for communicating data by an electronic device is provided. The method includes transmitting a signal including audio/video (A/V) data to a first external electronic device through a first communication module, while connected with the first external electronic device, generating data or a signal unrelated to the A/V data or receiving the data or signal unrelated to the A/V data from an external electronic device other than the first external electronic device, and providing an audio or a video through a display or an embedded sound device based on at least a portion of the data or the signal unrelated to the A/V data or transmitting the at least a portion of the data or the signal unrelated to the A/V data to a second external electronic device through a second communication module.

公开(公告)号：US10394648B2

公开(公告)日：2019-08-27

申请号：US15410752

申请日：2017-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-Hyung Song ,  Jangseok Choi

IPC: G06F11/10 ,  G11C11/4093 ,  G11C29/52

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

公开(公告)号：US09940991B2

公开(公告)日：2018-04-10

申请号：US15343977

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Joong Kim ,  Ho-young Song ,  Hoi-ju Chung ,  Ju-yun Jung ,  Sang-uhn Cha

IPC: G11C7/00 ,  G11C11/4096 ,  G06F3/06 ,  G11C7/10 ,  G11C11/406 ,  G11C29/02 ,  G11C29/04 ,  G11C29/52 ,  G11C29/50 ,  G11C29/12

CPC classification number: G11C11/4096 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1063 ,  G11C11/40611 ,  G11C11/40622 ,  G11C29/025 ,  G11C29/028 ,  G11C29/04 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0403 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/5002 ,  G11C2211/4068

Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

公开(公告)号：US20180046541A1

公开(公告)日：2018-02-15

申请号：US15286460

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US09747058B2

公开(公告)日：2017-08-29

申请号：US14730632

申请日：2015-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi-Won Oh ,  Ju-Yun Jung ,  Soo-Hyeong Kim ,  Hyun-Joong Kim

IPC: G11C29/00 ,  G06F3/06 ,  G11C5/02 ,  G11C7/10 ,  G11C8/00 ,  G11C5/04

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0659 ,  G11C5/02 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/00 ,  G11C29/76 ,  G11C2207/108

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.