公开(公告)号：US20190102302A1

公开(公告)日：2019-04-04

申请号：US15721223

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Karl I. Taht ,  Christopher B. Wilkerson ,  Ren Wang ,  James J. Greensky

IPC: G06F12/0831 ,  G06F12/0846 ,  G06F12/128

Abstract: Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

公开(公告)号：US10237171B2

公开(公告)日：2019-03-19

申请号：US15270377

申请日：2016-09-20

Applicant: INTEL CORPORATION

Inventor： Sameh Gobriel ,  Ren Wang ,  Eric K. Mann ,  Christian Maciocco ,  Tsung-Yuan C. Tai

IPC: H04L1/00 ,  H04L12/721 ,  H04L12/851 ,  H04L12/863 ,  H04L12/751 ,  H04L12/715

Abstract: Methods and apparatus for facilitating efficient Quality of Service (QoS) support for software-based packet processing by offloading QoS rate-limiting to NIC hardware. Software-based packet processing is performed on packet flows received at a compute platform, such as a general purpose server, and/or packet flows generated by local applications running on the compute platform. The packet processing includes packet classification that associates packets with packet flows using flow IDs, and identifying a QoS class for the packet and packet flow. NIC Tx queues are dynamically configured or pre-configured to effect rate limiting for forwarding packets enqueued in the NIC Tx queues. New packet flows are detected, and mapping data is created to map flow IDs associated with flows to the NIC Tx queues used to forward the packets associated with the flows.

公开(公告)号：US10229060B2

公开(公告)日：2019-03-12

申请号：US15369594

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Ren Wang ,  Namakkal N. Venkatesan ,  Patrick Lu

IPC: G06F12/0862

Abstract: Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected information to the cache, and a prefetch tuning buffer including tuning state for the set of candidate prefetcher algorithms, wherein the prefetcher is to adjust operation of the prefetcher algorithm based on the tuning state.

公开(公告)号：US10216668B2

公开(公告)日：2019-02-26

申请号：US15087154

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC: G06F13/24 ,  G06F13/36 ,  G06F13/40 ,  G06F12/1027

Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US20190056232A1

公开(公告)日：2019-02-21

申请号：US16166928

申请日：2018-10-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04W24/08 ,  H04W4/02 ,  H04B17/318

CPC classification number: G01C21/3453 ,  G01C21/3446 ,  H04B17/318 ,  H04W4/024 ,  H04W4/029 ,  H04W24/08

Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.

公开(公告)号：US20190044871A1

公开(公告)日：2019-02-07

申请号：US16144384

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Jiayu Hu ,  Cunming Liang ,  Ren Wang ,  Jr-Shian Tsai ,  Jingjing Wu ,  Zhaoyan Chen

IPC: H04L12/835 ,  H04L12/861 ,  H04L12/879 ,  G06F15/173

Abstract: Technologies for managing a single-producer and single-consumer ring include a producer of a compute node that is configured to allocate data buffers, produce work, and indicate that work has been produced. The compute node is configured to insert reference information for each of the allocated data buffers into respective elements of the ring and store the produced work into the data buffers. The compute node includes a consumer configured to request the produced work from the ring. The compute node is further configured to dequeue the reference information from each of the elements of the ring that correspond to the portion of data buffers in which the produced work has been stored, and set each of the elements of the ring for which the reference information has been dequeued to an empty (i.e., NULL) value. Other embodiments are described herein.

公开(公告)号：US20190042304A1

公开(公告)日：2019-02-07

申请号：US15829938

申请日：2017-12-03

Applicant: Intel Corporation

Inventor： Ren Wang ,  Janet Tseng ,  Jr-Shian Tsai ,  Tsung-Yuan Tai

IPC: G06F9/48 ,  H04L12/851

Abstract: Methods, apparatus, systems, and software for architectures and mechanisms to accelerate tuple-space search with integrated GPUs (Graphic Processor Units). One of the architectures employs GPU-side lookup table sorting, under which local and global hit count histograms are maintained for work groups, and sub-tables containing rules for tuple matching are re-sorted based on the relative hit rates of the different sub-tables. Under a second architecture, two levels of parallelism are implemented: packet-level parallelism and lookup table-parallelism. Under a third architecture, dynamic two-level parallel processing with pre-screen is implemented. Adaptive decision making mechanisms are also disclosed to select which architecture is optimal in view of multiple considerations, including application preferences, offered throughput, and available GPU resources. The architectures leverage utilization of both processor cores and GPU processing elements to accelerate tuple-space searches, including searches using wildcard masks.

公开(公告)号：US10042414B2

公开(公告)日：2018-08-07

申请号：US14129783

申请日：2013-10-01

Applicant: Intel Corporation

Inventor： Zhongghong Ou ,  Ren Wang

IPC: G06F1/26 ,  G06F1/32 ,  H04W52/02 ,  G06F9/48

Abstract: Technologies for scheduling network requests to reduce power consumption include a mobile computing device configured to receive a network request from a network application, and determine whether the network request is delayable, based on execution constraints of the application. Execution constraints may include required processing resources, acceptable latency, priority, application class, and others. If the request is delayable, the mobile computing device may delay the request until a threshold number of delayable requests are received, or until a non-delayable request is received. The mobile computing device performs the delayed request and any subsequently received requests concurrently. The execution constraints may be supplied by each network application, or may be determined by the mobile computing device through observation. Other embodiments are described and claimed.

公开(公告)号：US10019360B2

公开(公告)日：2018-07-10

申请号：US14866923

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Christopher B. Wilkerson

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0808 ,  G06F12/126 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/62 ,  Y02D10/13

Abstract: Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer optimization for network function virtualizations (NFVs) and other producer-consumer workloads. An apparatus embodiment includes a plurality of hardware processor cores each including a first cache, a second cache shared by the plurality of hardware processor cores, and a predictor circuit to track the number of inter-core versus intra-core accesses to a plurality of monitored cache lines in the first cache and control enablement of a cache line demotion instruction, such as a cache line LLC allocation (CLLA) instruction, based upon the tracked accesses. An execution of the cache line demotion instruction by one of the plurality of hardware processor cores causes a plurality of unmonitored cache lines in the first cache to be moved to the second cache, such as from L1 or L2 caches to a shared L3 or last level cache (LLC).

公开(公告)号：US09866479B2

公开(公告)日：2018-01-09

申请号：US14750921

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ren Wang ,  Dong Zhou ,  Bruce Richardson ,  George W. Kennedy ,  Christian Maciocco ,  Sameh Gobriel ,  Tsung-Yuan C. Tai

IPC: H04L12/743 ,  H04L12/851 ,  H04L12/819

CPC classification number: H04L45/7453 ,  H04L47/21 ,  H04L47/2483

Abstract: Technologies for supporting concurrency of a flow lookup table at a network device. The flow lookup table includes a plurality of candidate buckets that each includes one or more entries. The network device includes a flow lookup table write module configured to perform a displacement operation of a key/value pair to move the key/value pair from one bucket to another bucket via an atomic instruction and increment a version counter associated with the buckets affected by the displacement operation. The network device additionally includes a flow lookup table read module to check the version counters during a lookup operation on the flow lookup table to determine whether a displacement operation is affecting the presently read value of the buckets. Other embodiments are described herein and claimed.