公开(公告)号：US10067713B2

公开(公告)日：2018-09-04

申请号：US15243446

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Guy L. Guthrie ,  Cathy May ,  William J. Starke ,  Derek E. Williams

IPC: G06F3/06 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F9/30 ,  G06F9/38

Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.

公开(公告)号：US09727489B1

公开(公告)日：2017-08-08

申请号：US15288767

申请日：2016-10-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0864 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a distance from the cache memory to a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the distance.

公开(公告)号：US09678812B2

公开(公告)日：2017-06-13

申请号：US14579681

申请日：2014-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lakshminarayana B. Arimilli ,  John D. Irish ,  William J. Starke ,  Randal C. Swanberg

IPC: G06F9/54 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/467 ,  G06F9/4881 ,  G06F9/54 ,  G06F9/544

Abstract: In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.

公开(公告)号：US09563558B2

公开(公告)日：2017-02-07

申请号：US14472056

申请日：2014-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/52 ,  G06F13/376 ,  G06F12/08 ,  G06F12/12 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/522 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0897 ,  G06F12/128 ,  G06F2212/284 ,  G06F2212/6042

Abstract: A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.

Abstract translation: 用于操作数据处理系统的高速缓冲存储器的技术包括创建相应的污染向量，以跟踪由相关联的处理器核心执行的多个并发线程当前被驻留在高速缓存存储器中的存储操作所污染的哪一个。 基于污染向量设置缓存存储器的存储队列的依赖性数据结构中的依赖关系，以减少不必要的排序效应。 存储操作根据依赖关系数据结构指示的依赖关系从存储队列中发出。

公开(公告)号：US09495314B2

公开(公告)日：2016-11-15

申请号：US14311467

申请日：2014-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul A. Ganfield ,  Guy L. Guthrie ,  John T. Hollaway, Jr. ,  David J. Krolak ,  Charles F. Marino ,  Praveen S. Reddy ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F3/00 ,  G01R31/08 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36 ,  G01R31/08 ,  G06F3/00 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

公开(公告)号：US09495312B2

公开(公告)日：2016-11-15

申请号：US14136958

申请日：2013-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul A. Ganfield ,  Guy L. Guthrie ,  John T. Hollaway, Jr. ,  David J. Krolak ,  Charles F. Marino ,  Praveen S. Reddy ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F3/00 ,  G01R31/08 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36 ,  G01R31/08 ,  G06F3/00 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract translation: 在一个或多个实施例中，所描述的一个或多个系统，设备，方法和/或处理可以经由互连将速率主控命令发送到多个处理节点中的至少一个; 确定接收到与速率主命令相关联的指示丢弃命令的消息; 确定与丢弃的命令相关联的计数满足阈值; 并且响应于确定所述计数满足所述阈值，经由所述互连件向所述处理节点提供指示命令速率的信号。 此外，可以响应于确定接收到消息而增加计数。 多个处理节点中的至少一个可以经由互连接收指示命令速率的信号，并且可以经由互连来发出推测命令中的命令速率。

公开(公告)号：US09367458B2

公开(公告)日：2016-06-14

申请号：US13777028

申请日：2013-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  David W. Cummings ,  Michael S. Siegel ,  William J. Starke ,  Jeff A. Stuecheli

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/06 ,  G06F13/16 ,  G06F12/14 ,  G06F3/12 ,  G06F12/02

CPC classification number: G06F12/0815 ,  G06F3/122 ,  G06F12/0284 ,  G06F12/0638 ,  G06F12/082 ,  G06F12/0831 ,  G06F12/1416 ,  G06F13/1615

Abstract: A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.

公开(公告)号：US09106258B2

公开(公告)日：2015-08-11

申请号：US14087801

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Benjiman L. Goodman ,  Harrison M. McCreary ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G11C29/00 ,  H03M13/09

CPC classification number: H03M13/09 ,  G06F11/1004 ,  G06F11/1016

Abstract: A bypass mechanism allows a memory controller to transmit requested data to an interconnect before the data's error code has been decoded, e.g., a cyclical redundancy check (CRC). The tag, tag CRC, data, and data CRC are pipelined from DRAM in four frames, each having multiple clock cycles. The tag includes a bypass bit indicating whether data transmission to the interconnect should begin before CRC decoding. After receiving the tag CRC, the controller decodes it and reserves a request machine which sends a transmit request signal to inform the interconnect that data is available. Once the transmit request is granted by the interconnect, the controller can immediately start sending the data, before decoding the data CRC. So long as no error is found, the controller completes transmission of the data to the interconnect, including providing an indication that the data as transmitted is error-free.

Abstract translation: 旁路机制允许存储器控制器在数据的错误代码被解码之前（例如，循环冗余校验（CRC））将所请求的数据发送到互连。 标签，标签CRC，数据和数据CRC在DRAM中以四帧流水线，每帧具有多个时钟周期。 标签包括一个旁路位，指示在CRC解码之前是否应开始到互连的数据传输。 在接收到标签CRC之后，控制器对其进行解码并保留发送发送请求信号以通知互连的数据可用的请求机。 一旦通过互连授予发送请求，控制器可以在解码数据CRC之前立即开始发送数据。 只要没有发现错误，控制器完成数据到互连的传输，包括提供发送的数据是无差错的指示。

公开(公告)号：US09058260B2

公开(公告)日：2015-06-16

申请号：US13856937

申请日：2013-04-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John S. Dodson ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Eric E. Retter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: H03M13/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1004

Abstract: In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.

Abstract translation: 在数据处理系统中，存储器子系统检测是否存在至少一个潜在的瞬态条件，其将阻止及时地对针对相关系统存储器的一个或多个存储器访问请求进行维护。 响应于检测到至少一个这样的潜在瞬态条件，存储器系统识别受至少一个潜在瞬态条件影响的第一读取请求。 响应于识别读取请求，存储器子系统通过向请求源发送伪数据和数据错误指示符来向请求源发信号，以发出相同目标地址的第二读取请求。

公开(公告)号：US20150100731A1

公开(公告)日：2015-04-09

申请号：US14048474

申请日：2013-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy Lynn Guthrie ,  Steven R. Kunkel ,  Hien Minh Le ,  Geraint North ,  William J. Starke

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0802 ,  G06F11/1405 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/152

Abstract: A technique of operating a data processing system, includes logging addresses for cache lines modified by a producer core in a data array of a producer cache to create a high-availability (HA) log for the producer core. The technique also includes moving the HA log directly from the producer cache to a consumer cache of a consumer core and moving HA data associated with the addresses of the HA log directly from the producer cache to the consumer cache. The HA log corresponds to a cache line that includes multiple of the addresses. Finally, the technique includes processing, by the consumer core, the HA log and the HA data for the data processing system.

Abstract translation: 操作数据处理系统的技术包括记录由生产者高速缓存的数据阵列中的生产者核心修改的高速缓存行的地址，以为生产者核心创建高可用性（HA）日志。 该技术还包括将HA日志从生产者缓存直接移动到消费者核心的消费者缓存，并将与HA日志的地址相关联的HA数据直接从生产者缓存移动到消费者缓存。 HA日志对应于包含多个地址的高速缓存行。 最后，该技术包括消费者核心处理数据处理系统的HA日志和HA数据。