公开(公告)号：US20160049337A1

公开(公告)日：2016-02-18

申请号：US14919796

申请日：2015-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/311 ,  H01L21/225 ,  H01L21/033 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

公开(公告)号：US09087927B2

公开(公告)日：2015-07-21

申请号：US14521743

申请日：2014-10-23

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC: H01L49/02 ,  H01L21/84 ,  H01L27/108 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract translation: 在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。 电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。 ％至20重量％ ％。

公开(公告)号：US09059315B2

公开(公告)日：2015-06-16

申请号：US13732455

申请日：2013-01-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/823857

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

公开(公告)号：US20150069525A1

公开(公告)日：2015-03-12

申请号：US14541182

申请日：2014-11-14

Applicant: International Business Machines Corporation

Inventor： Charlotte D. Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC: H01L27/088 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

Abstract translation: 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

公开(公告)号：US20150044853A1

公开(公告)日：2015-02-12

申请号：US14521743

申请日：2014-10-23

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract translation: 在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。 电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。 ％至20重量％ ％。

公开(公告)号：US20150021699A1

公开(公告)日：2015-01-22

申请号：US13945095

申请日：2013-07-18

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/0886 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4908

Abstract: A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one workfunction material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks straddling the semiconductor fins.

Abstract translation: 在包括一种或多种半导体材料的半导体鳍片上形成高介电常数（高k）栅极电介质层。 形成图案化扩散阻挡金属氮化物层以覆盖至少一个通道，而不覆盖至少另一个通道。 在高k栅极电介质层和扩散阻挡金属氮化物层的物理暴露部分上形成阈值电压调整氧化物层。 执行退火以将阈值电压调节氧化物层的材料驱动到本征通道和高k栅极电介质层之间的界面，从而形成阈值电压调节氧化物部分。 形成至少一个功函数材料层，并用高k栅极介电层和阈值电压调整氧化物部分进行图案化以形成跨越半导体鳍片的多种类型的栅叠层。