公开(公告)号：US20160013181A1

公开(公告)日：2016-01-14

申请号：US14864091

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L27/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US20150371893A1

公开(公告)日：2015-12-24

申请号：US14307604

申请日：2014-06-18

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee ,  Richard A. Wachnik

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76283 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit.

Abstract translation: 在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成掩埋导电层。 形成横向围绕埋入导电层的一部分的深隔离沟槽，并且至少填充有介电衬垫以形成深电容器沟槽隔离结构。 通过结构的接触通过掩埋绝缘体层和顶部半导体层形成，并且形成在掩埋导电层的构成掩埋导电导管的部分上。 深电容器沟槽隔离结构可以与至少一个深沟槽电容器同时形成。 可以使用顶部半导体层的图案化部分作为用于信号传输的附加导电管道。 此外，深电容器沟槽隔离结构可以包括导电部分，导电部分可被电偏置以控制包括埋入导电导管的信号路径的阻抗。

公开(公告)号：US08963228B2

公开(公告)日：2015-02-24

申请号：US13865267

申请日：2013-04-18

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L21/336 ,  H01L27/12 ,  H01L27/105

CPC classification number: H01L27/1203 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/7883

Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.

Abstract translation: 提供用于集成SOI CMOS FET和NVRAM存储器件的结构和方法。 该结构包括含有半导体衬底，SOI层和形成在半导体衬底和SOI层之间的BOX层的SOI衬底。 SOI衬底包括预定义的SOI器件和NVRAM器件区域。 在SOI器件区域中形成SOI FET。 SOI FET包括BOX层和SOI层的部分，SOI FET栅极电介质层和栅极导体层。 该结构还包括形成在NVRAM器件区域中的NVRAM器件。 NVRAM器件包括隧道氧化物，浮动栅极，阻塞氧化物和控制栅极层。 隧道氧化物层与SOI器件区域中BOX层的部分共面。 浮置栅极层与SOI器件区域中的半导体层的部分共面。

公开(公告)号：US08667448B1

公开(公告)日：2014-03-04

申请号：US13688595

申请日：2012-11-29

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: Embodiments include a method for providing a local maximum operating voltage on an integrated circuit. The method includes determining a gate-to-contact reliability for each of the plurality of regions and calculating a local maximum voltage for each of the plurality of regions based on the gate-to-contact reliability. Based on a determination that the local maximum voltage in one of the plurality of regions is greater than a maximum voltage, the method includes setting the local maximum operating voltage to the maximum voltage. Based on a determination that the local maximum voltage in one of the plurality of regions is less than the maximum voltage, the method includes setting the local maximum operating voltage to the local maximum voltage.

Abstract translation: 实施例包括用于在集成电路上提供局部最大工作电压的方法。 该方法包括确定多个区域中的每个区域的栅极 - 接触可靠性，并且基于栅极 - 接触可靠性计算多个区域中的每个区域的局部最大电压。 基于多个区域中的一个区域中的局部最大电压大于最大电压的判定，该方法包括将局部最大工作电压设定为最大电压。 基于多个区域中的一个区域中的局部最大电压小于最大电压的判定，该方法包括将局部最大工作电压设定为局部最大电压。