公开(公告)号：US09406762B2

公开(公告)日：2016-08-02

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20160181365A1

公开(公告)日：2016-06-23

申请号：US14577451

申请日：2014-12-19

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/739

CPC classification number: H01L29/1037 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

Abstract translation: 半导体器件可以包括具有第一导电类型的漂移区域，具有第一导电类型的源极区域和与漂移区域相邻并且与源极区域相邻设置的具有第二导电类型的阱区域。 阱区域可以包括具有第二导电类型的沟道区域，其邻近源极区域设置并且靠近半导体器件单元的表面。 沟道区域可以包括包括至少一个突起的非均匀边缘。

公开(公告)号：US20150372088A1

公开(公告)日：2015-12-24

申请号：US14313785

申请日：2014-06-24

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/1095 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7835

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is substantially disposed over the center of the semiconductor device cell. The SSBC also includes at least one source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

Abstract translation: 在碳化硅（SiC）半导体层的表面上制造半导体器件单元的方法包括在SiC半导体层的表面上形成半导体器件单元的分段源极和体接触（SSBC）。 SSBC包括设置在半导体层的表面上并且靠近半导体器件单元的体接触区域的体接触部分，其中主体接触部分基本上设置在半导体器件单元的中心之上。 SSBC还包括设置在半导体层的表面上并且靠近半导体器件单元的源极接触区域的至少一个源极接触部分，其中至少一个源极接触部分仅部分地围绕SSBC的主体接触部分。

公开(公告)号：US20150155355A1

公开(公告)日：2015-06-04

申请号：US14097075

申请日：2013-12-04

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L23/544 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7832 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

Abstract translation: 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。 半导体器件包括将第一深度延伸到位于漂移区上方的外延半导体层的表面的阱区。 该器件包括邻近外延半导体层中的阱区定位的结场效应晶体管（JFET）区域。 该器件还包括将第二深度延伸到JFET区域中的沟槽，其中该沟槽包括底部和与该外延半导体层的表面成一定角度向下延伸到底部的侧壁。

公开(公告)号：US09024328B2

公开(公告)日：2015-05-05

申请号：US13934053

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/22 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7827

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract translation: 半导体器件包括设置在（0001）取向的SiC衬底上的碳化硅（SiC）漂移层。 SiC漂移层具有包括平行于半导体器件的沟道的长度定向的多个重复特征的非平面表面。 此外，沟道区设置在SiC漂移层的特定结晶平面中。

公开(公告)号：US20150028469A1

公开(公告)日：2015-01-29

申请号：US13950736

申请日：2013-07-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Rui Zhou ,  Peter Almern Losee

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L27/0248 ,  H01L2924/0002

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract translation: 提出了一种单片集成半导体组件。 半导体组件包括包括硅（Si）的衬底，并且在衬底上制造氮化镓（GaN）半导体器件。 半导体组件还包括在衬底中或衬底上制造的至少一个瞬态电压抑制器（TVS）结构，其中TVS结构与GaN半导体器件电接触。 当跨越GaN半导体器件的施加电压大于阈值电压时，TVS结构被配置为以穿通模式，雪崩模式或其组合工作。 还提出了制造单片集成半导体组件的方法。

公开(公告)号：US20150008446A1

公开(公告)日：2015-01-08

申请号：US13933366

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Stacey Joy Kennerly

IPC: H01L21/04 ,  H01L29/16

CPC classification number: H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm−2 to about 12×1013 cm−2. Semiconductor devices are also presented.

Abstract translation: 提出了制造半导体器件的方法。 该方法包括提供包括碳化硅的半导体层，其中半导体层包括掺杂有第一掺杂剂类型的第一区域。 该方法还包括使用单个注入掩模和基本相似的注入剂量来注入具有第二掺杂剂类型的半导体层，以在半导体层中形成第二区域和结终止延伸（JTE），其中注入剂量在一个范围内 从约2×10 13 cm -2至约12×10 13 cm -2。 还提供了半导体器件。