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    Mobility Enhanced FET Devices
    61.
    发明申请
    Mobility Enhanced FET Devices 审中-公开
    移动增强型FET器件

    公开(公告)号：US20090298244A1

    公开(公告)日：2009-12-03

    申请号：US12537275

    申请日：2009-08-07

    申请人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

    发明人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/7845

    摘要： NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

    摘要翻译： 具有单独应力通道区域的NFET和PFET器件及其制造方法。 公开了一种FET，其包括栅极，该栅极包括处于第一应力状态的金属。 FET还包括托管在单晶Si基材料中的沟道区域，该沟道区域被栅极覆盖并处于第二应力状态。 沟道区域的第二应力状态与包括在栅极中的金属的第一应力状态相反。 NFET通道通常处于应力的拉伸状态，而PFET通道通常处于应力的压缩状态。 制造方法包括通过物理气相沉积（PVD）沉积金属层，使得层处于应力状态。

    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH
    62.
    发明申请
    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH 失效
    具有自对准独立门控阀的门控方案

    公开(公告)号：US20090203200A1

    公开(公告)日：2009-08-13

    申请号：US12027444

    申请日：2008-02-07

    申请人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    发明人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    IPC分类号： H01L21/027

    CPC分类号： H01L21/32139 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823828

    摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

    摘要翻译： 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

    STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C
    64.
    发明申请
    STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
    用于制造SiGe和/或Si：C的栅极应力工程的散装硅和SOI MOS器件中的分离自由应力通道的结构和方法

    公开(公告)号：US20090149010A1

    公开(公告)日：2009-06-11

    申请号：US12352504

    申请日：2009-01-12

    申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

    发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

    IPC分类号： H01L21/18

    CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

    摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

    摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

    FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS
    66.
    发明申请
    FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS 有权
    FINFET结构使用不同的门电介质材料和门电极材料

    公开(公告)号：US20090057765A1

    公开(公告)日：2009-03-05

    申请号：US11847573

    申请日：2007-08-30

    申请人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

    发明人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/785

    摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

    摘要翻译： 半导体结构包括第一finFET和第二finFET。 第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。 在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

    Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C
    69.
    发明授权
    Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C 有权
    通过SiGe和/或Si：C的栅极应力工程制造体硅和SOI CMOS器件中无位错应力通道的结构和方法

    公开(公告)号：US07476580B2

    公开(公告)日：2009-01-13

    申请号：US11931387

    申请日：2007-10-31

    申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

    发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

    摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

    摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

    Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film
    70.
    发明授权
    Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film 有权
    用强调膜增强nMOSFET和pMOSFET性能的方法和结构

    公开(公告)号：US07476579B2

    公开(公告)日：2009-01-13

    申请号：US11560925

    申请日：2006-11-17

    申请人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

    发明人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

    IPC分类号： H01L21/336

    CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

    摘要翻译： 用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。