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261 条记录 (耗时 0.03 秒)

    Capacitance measurement method employing floating gate of semiconductor device
    62.
    发明授权
    Capacitance measurement method employing floating gate of semiconductor device 失效
    采用半导体器件浮栅的电容测量方法

    公开(公告)号：US07751995B2

    公开(公告)日：2010-07-06

    申请号：US11830210

    申请日：2007-07-30

    申请人： Jong Min Kim

    发明人： Jong Min Kim

    IPC分类号： G01R5/28

    CPC分类号： G01R27/2605

    摘要： A capacitance measurement method employing a floating gate of a semiconductor device in a circuit having a MOSFET in which a drain is connected to a ground and a source and a gate are connected to each other, and a capacitor having a capacitance Cr connected to the gate, includes: obtaining a slope S from a relationship between voltage Vs of the source and a voltage Vf applied to the capacitor; setting a standard slope S0 as a y-intercept of a first-order linear equation obtained from a relationship between the slope S depending on the source current Is and the Vo(Is); and calculating a gate-to-drain overlap capacitance Cdgo of the MOSFET based on a capacitance Cr of the capacitor and the standard slop S0.

    摘要翻译： 在具有MOSFET的电路中使用半导体器件的浮置栅极的电容测量方法，其中漏极连接到地和源极和栅极彼此连接，并且具有连接到栅极的电容Cr的电容器 包括：从源极的电压Vs与施加到电容器的电压Vf之间的关系获得斜率S; 将标准斜率S0设定为根据源电流Is和Vo（Is）之间的斜率S之间的关系获得的一阶线性方程的y截距; 以及基于电容器的电容Cr和标准斜率S0来计算MOSFET的栅 - 漏重叠电容Cdgo。

    Semiconductor Device and Method for Fabricating the Same
    63.
    发明申请
    Semiconductor Device and Method for Fabricating the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20100155841A1

    公开(公告)日：2010-06-24

    申请号：US12631438

    申请日：2009-12-04

    申请人： Jong Min Kim

    发明人： Jong Min Kim

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66659

    摘要： A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a second well, implanting second conduction type impurities into the second well to form an impurity region, forming a gate on the semiconductor substrate, and implanting second conduction type impurities to form a drain region in the impurity region on one side of the gate.

    摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括将第一导电型杂质注入到半导体衬底中以形成第一阱，将第二导电型杂质注入到第一阱中以形成第二阱，将第二导电型杂质注入到第二阱中以形成杂质区，形成 栅极，并且在栅极的一侧的杂质区域中注入第二导电型杂质以形成漏区。

    Method of manufacturing a semiconductor device
    65.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07723190B2

    公开(公告)日：2010-05-25

    申请号：US11647691

    申请日：2006-12-28

    申请人： Gyu Gwang Sim ,  Jong Min Kim

    发明人： Gyu Gwang Sim ,  Jong Min Kim

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7828

    摘要： Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.

    摘要翻译： 公开了一种具有提高集成度的垂直沟槽栅极结构的半导体器件及其制造方法。 半导体器件包括在第一导电类型衬底上具有第二导电类型的外延层，该第一导电类型衬底具有有源区和隔离区，隔离区中的沟槽，在外延层中的第二导电类型的第一区， 沟槽，沟槽中预定深度处的隔离层，沿着沟槽的上侧部分的栅极绝缘层，沟槽上部的栅极电极，有源区域中的主体区域，主体上的源极电极 区域，位于栅电极的相对侧部的体区的上部的源极区域和位于衬底的背面的漏电极。

    Image Sensor and Method for Manufacturing the Same
    68.
    发明申请
    Image Sensor and Method for Manufacturing the Same 审中-公开
    图像传感器及其制造方法

    公开(公告)号：US20100091155A1

    公开(公告)日：2010-04-15

    申请号：US12575855

    申请日：2009-10-08

    申请人： HEE SUNG SHIM ,  Joon Hwang ,  Jong Min Kim

    发明人： HEE SUNG SHIM ,  Joon Hwang ,  Jong Min Kim

    IPC分类号： H04N5/335 ,  H01L21/768

    CPC分类号： H01L27/14636 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/1469

    摘要： An image sensor is provided. The image sensor comprises a readout circuitry, an interconnection, an insulating layer, an electrode, and an image sensing device. The readout circuitry is disposed in a first substrate. The interconnection is disposed over the first substrate and electrically connected to the readout circuitry. The insulating layer is disposed over the interconnection. The electrode is disposed on the insulating layer. The image sensing device is disposed on the electrode. The electrode and the interconnection provide a capacitive coupling of the image sensing device to the readout circuitry so that a contact formation process to contact the photodiode to the interconnection can be omitted.

    摘要翻译： 提供图像传感器。 图像传感器包括读出电路，互连，绝缘层，电极和图像感测装置。 读出电路设置在第一衬底中。 互连设置在第一基板上并电连接到读出电路。 绝缘层设置在互连上。 电极设置在绝缘层上。 图像感测装置设置在电极上。 电极和互连提供了图像感测装置与读出电路的电容耦合，从而可以省略将光电二极管与互连接触的触点形成过程。

    ELECTROSTATIC DISCHARGE PROJECTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    69.
    发明申请
    ELECTROSTATIC DISCHARGE PROJECTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    静电放电投影半导体器件及其制造方法

    公开(公告)号：US20100084711A1

    公开(公告)日：2010-04-08

    申请号：US12545271

    申请日：2009-08-21

    申请人： Jong-Min Kim ,  Jong-Kyu Song ,  San-Hong Kim

    发明人： Jong-Min Kim ,  Jong-Kyu Song ,  San-Hong Kim

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical device, including a semiconductor device such an electrostatic discharge protection semiconductor device, and a method for manufacturing the same. An electrostatic discharge protection semiconductor device may include a substrate and a gate in and/or over the substrate. The gate may be multi-layered, and may include a gate oxide layer and a gate electrode. An electrostatic discharge protection semiconductor device may include a source region formed in and/or over a predetermined area of the substrate on a side of the gate, and a plurality of drain regions which may be sequentially multi-layered in and/or over the substrate on an opposing side of the gate in a vertical direction. At least one drain region may be overlapped with the gate in a horizontal direction.

    摘要翻译： 包括诸如静电放电保护半导体器件的半导体器件的电子器件及其制造方法。 静电放电保护半导体器件可以包括衬底和衬底中和/或之上的栅极。 栅极可以是多层的，并且可以包括栅极氧化物层和栅电极。 静电放电保护半导体器件可以包括形成在栅极侧上的衬底的预定区域中和/或之上的源极区域，以及可以在衬底中和/或衬底上顺序地多层的多个漏极区域 在垂直方向上在门的相对侧上。 至少一个漏极区域可以在水平方向上与栅极重叠。