公开(公告)号：US07723190B2

公开(公告)日：2010-05-25

申请号：US11647691

申请日：2006-12-28

申请人： Gyu Gwang Sim ,  Jong Min Kim

发明人： Gyu Gwang Sim ,  Jong Min Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7828

摘要： Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.

摘要翻译： 公开了一种具有提高集成度的垂直沟槽栅极结构的半导体器件及其制造方法。 半导体器件包括在第一导电类型衬底上具有第二导电类型的外延层，该第一导电类型衬底具有有源区和隔离区，隔离区中的沟槽，在外延层中的第二导电类型的第一区， 沟槽，沟槽中预定深度处的隔离层，沿着沟槽的上侧部分的栅极绝缘层，沟槽上部的栅极电极，有源区域中的主体区域，主体上的源极电极 区域，位于栅电极的相对侧部的体区的上部的源极区域和位于衬底的背面的漏电极。

公开(公告)号：US07944001B2

公开(公告)日：2011-05-17

申请号：US11869378

申请日：2007-10-09

申请人： Kyong-Tae Chu ,  Gyu-Gwang Sim ,  Jong-Min Kim

发明人： Kyong-Tae Chu ,  Gyu-Gwang Sim ,  Jong-Min Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power metal oxide silicon field effect transistor in which sources are connected to each other, a single source supplies electrons to two channels, a contact surface between the source and a channel is variously changed to be maximized such that large current flows in a small area, and an electrical field is not concentrated to a gate edge.

摘要翻译： 一种功率金属氧化物硅场效应晶体管，其中源极彼此连接，单个源将电子提供给两个通道，源极和沟道之间的接触表面被不同地改变为最大化，使得大电流在小面积中流动 并且电场不集中到栅极边缘。

公开(公告)号：US20080087953A1

公开(公告)日：2008-04-17

申请号：US11869378

申请日：2007-10-09

申请人： Kyong-Tae CHU ,  Gyu-Gwang Sim ,  Jong-Min Kim

发明人： Kyong-Tae CHU ,  Gyu-Gwang Sim ,  Jong-Min Kim

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power metal oxide silicon field effect transistor in which sources are connected to each other, a single source supplies electrons to two channels, a contact surface between the source and a channel is variously changed to be maximized such that large current flows in a small area, and an electrical field is not concentrated to a gate edge.

摘要翻译： 一种功率金属氧化物硅场效应晶体管，其中源极彼此连接，单个源将电子提供给两个通道，源极和沟道之间的接触表面被不同地改变为最大化，使得大电流在小面积中流动 并且电场不集中到栅极边缘。

公开(公告)号：US20080061364A1

公开(公告)日：2008-03-13

申请号：US11898296

申请日：2007-09-11

申请人： Gyu Gwang Sim ,  Jong Min Kim

发明人： Gyu Gwang Sim ,  Jong Min Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66734

摘要： A trench type MOS transistor and a method for manufacturing the trench type MOS transistor are disclosed. In one aspect, the total capacitance between a gate electrode and a drain region of the trench type MOS transistor can be reduced. In particular, a PN junction is formed in the gate electrode to reduce the total capacitance between the gate electrode and the drain region.

摘要翻译： 公开了沟槽型MOS晶体管及其制造方法。 在一个方面，可以减小沟槽型MOS晶体管的栅极电极和漏极区域之间的总电容。 特别地，在栅电极中形成PN结以减小栅极电极和漏极区域之间的总电容。