公开(公告)号：US07129541B2

公开(公告)日：2006-10-31

申请号：US10945246

申请日：2004-09-20

申请人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/113 ,  H01L31/119

CPC分类号： H01L29/78696 ,  H01L29/42336 ,  H01L29/42384 ,  H01L29/66787 ,  H01L29/66825

摘要： A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

摘要翻译： 在半导体衬底的有源区域上的场效应晶体管包括半导体衬底的垂直突出的薄体部分和至少部分地在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直取向的栅电极。 晶体管还包括围绕垂直取向的栅电极的上部的绝缘层和绝缘层上的横向取向的栅电极，并连接到垂直取向的栅电极的顶部。 因此，T形栅电极被限定为具有在半导体衬底的顶表面上的横向部分，并且具有至少部分至少部分在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直部分。

公开(公告)号：US20060186446A1

公开(公告)日：2006-08-24

申请号：US11349287

申请日：2006-02-06

申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Jae-Man Yoon

发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Jae-Man Yoon

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

摘要翻译： 在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。 可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

公开(公告)号：US20060175669A1

公开(公告)日：2006-08-10

申请号：US11339126

申请日：2006-01-25

申请人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

摘要： Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

摘要翻译： 提供了包括具有金属栅极的FinFET的半导体器件及其制造方法。 半导体器件包括：形成在半导体衬底中并从半导体衬底的表面突出的有源区; 翅片，其包括由有源区域的表面形成的第一和第二突起，并且基于形成在有源区域中的中心沟槽并且使用第一和第二突起的上表面和侧面作为沟道区域彼此平行; 形成在包括所述鳍片的所述有源区域上的栅极绝缘层; 形成在所述栅极绝缘层上的金属栅电极; 形成在所述金属栅电极的侧壁上的栅极间隔; 以及在金属栅电极的两侧旁边的有源区域中形成的源极和漏极。 这里，金属栅电极包括与栅极间隔物和栅极绝缘层接触的阻挡层和形成在阻挡层上的金属层。

公开(公告)号：US20060157753A1

公开(公告)日：2006-07-20

申请号：US11335390

申请日：2006-01-19

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7923

摘要： Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.

摘要翻译： 描述了多位非易失性存储器件及其相关制造方法。 在一些多位非易失性存储器件中，半导体衬底具有限定在其中的凹陷区域。 可以包括ONO层的绝缘层被配置为在其中的编程区域内存储数据，并且覆盖凹部区域的侧壁和下表面。 栅电极位于凹陷区域的绝缘层上。 半导体衬底中至少有一对杂质区。 杂质区域与凹陷区域中的绝缘层的侧表面相邻，并且相对于栅电极的中心形成小于120°的相对角度。

公开(公告)号：US20060121687A1

公开(公告)日：2006-06-08

申请号：US11285300

申请日：2005-11-23

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

摘要翻译： 在具有多桥通道的半导体器件及其制造方法中，该器件包括从半导体衬底的表面突出并分别具有源极和漏极区域的第一和第二半导体柱， 其部分，连接第一和第二半导体柱的上侧部分的沟道半导体层，沟道半导体层和半导体衬底上的栅极绝缘层，围绕至少一部分沟道半导体层的栅极绝缘层，栅电极 在所述栅绝缘层上包围所述沟道半导体层之间的区域的至少一部分，以及形成在所述沟道半导体层之间的接合辅助层，与所述栅电极层接触的所述结辅助层和所述第一和第二栅极的上侧部分 半导体柱，并且具有与沟道半导体层相同的宽度。

公开(公告)号：US20060120148A1

公开(公告)日：2006-06-08

申请号：US11238381

申请日：2005-09-29

申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US20050032322A1

公开(公告)日：2005-02-10

申请号：US10909471

申请日：2004-08-02

申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

IPC分类号： H01L29/786 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76 ,  H01L21/3205

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

公开(公告)号：US20120161247A1

公开(公告)日：2012-06-28

申请号：US13411699

申请日：2012-03-05

申请人： Eun-Jung Yun ,  Sung-yung Lee ,  Min-sang Kim ,  Sung-min Kim

发明人： Eun-Jung Yun ,  Sung-yung Lee ,  Min-sang Kim ,  Sung-min Kim

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/42392

摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。

公开(公告)号：US08198704B2

公开(公告)日：2012-06-12

申请号：US12710378

申请日：2010-02-23

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L29/06 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/02667 ,  H01L21/02639 ,  H01L21/2026 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

摘要翻译： 在一个实施例中，制造具有晶体半导体层的半导体器件的方法包括制备半导体衬底并在半导体衬底上形成预活性图案。 预活性图案包括阻挡图案和非单晶半导体图案。 牺牲非单晶半导体层覆盖预活性图案和半导体衬底。 通过使牺牲非单晶半导体层和非单晶半导体图案结晶，使用半导体衬底作为晶种层，将牺牲非单晶半导体层和非单晶半导体图案改变为牺牲晶体 半导体层和晶体半导体图案。 晶体半导体图案和势垒图案构成活性图案。 去除牺牲晶体半导体层。

公开(公告)号：US07897463B2

公开(公告)日：2011-03-01

申请号：US12651688

申请日：2010-01-04

申请人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

发明人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/7831

摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

摘要翻译： 晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。 相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。 相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。 相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。 栅电极设置在第一和第二栅极绝缘体之间。 第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。