公开(公告)号：US20220320140A1

公开(公告)日：2022-10-06

申请号：US17223050

申请日：2021-04-06

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Erh-Kun LAI ,  Hsiang-Lan Lung

IPC分类号： H01L27/11597 ,  H01L27/1159 ,  H01L21/285 ,  H01L21/764 ,  H01L29/06 ,  H01L29/45

摘要： A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

公开(公告)号：US20220310534A1

公开(公告)日：2022-09-29

申请号：US17582147

申请日：2022-01-24

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Mengmeng WANG ,  Hsin-Pin HUANG ,  Qiang ZHANG

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/764 ,  H01L21/768

摘要： The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure comprises: a substrate, in which a first protective structure is formed, is provided; a first dielectric layer is formed on the substrate; and a second protective structure is formed in the first dielectric layer and the substrate. A projection of the second protective structure and a projection of the first protective structure in a direction perpendicular to a surface of the substrate are at least partially overlapped, and there is a spacing between a projection of the second protective structure and a projection of the first protective structure in a direction along the surface of the substrate.

公开(公告)号：US20220310387A1

公开(公告)日：2022-09-29

申请号：US17701433

申请日：2022-03-22

申请人： ASM IP Holding B.V.

发明人： WanGyu Lim ,  HeeSung Kang ,  JaeOk Ko ,  JaeBin Ahn ,  Sunja Kim ,  YoungJae Kim ,  DongHyun Ko

IPC分类号： H01L21/02 ,  H01L21/764

摘要： A substrate processing method of forming an air gap includes: forming deposition inhibitor sites in a lower space between a first protrusion and a second protrusion; and forming film-forming sites and an interlayer insulating layer on the first protrusion and the second protrusion, wherein the interlayer insulating layer is selectively formed in an upper space between the first protrusion and the second protrusion by the deposition inhibitor sites and the film-forming layer, and thus an air gap is formed between the first protrusion and the second protrusion.

公开(公告)号：US11456307B2

公开(公告)日：2022-09-27

申请号：US16527503

申请日：2019-07-31

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang Chen ,  Shengfen Chiu

IPC分类号： H01L27/11524 ,  H01L21/768 ,  H01L49/02 ,  H01L27/11529 ,  H01L27/11539 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/311 ,  H01L21/764 ,  H01L27/11534 ,  H01L29/06 ,  H01L29/788

摘要： A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

公开(公告)号：US20220285533A1

公开(公告)日：2022-09-08

申请号：US17465762

申请日：2021-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin LEE ,  Choh Fei YEAP ,  Da-Wen LIN ,  Chih-Chieh YEH

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764

摘要： A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

公开(公告)号：US11430689B2

公开(公告)日：2022-08-30

申请号：US16154907

申请日：2018-10-09

申请人： Cypress Semiconductor Corporation

发明人： Rinji Sugino ,  Fei Wang

IPC分类号： H01L21/764

摘要： A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

公开(公告)号：US20220238646A1

公开(公告)日：2022-07-28

申请号：US17157269

申请日：2021-01-25

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Mark D. LEVY ,  Siva P. ADUSUMILLI ,  Johnatan A. KANTAROVSKY ,  Vibhor JAIN

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/06 ,  H01L21/308 ,  H01L21/764

摘要： The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US11387365B2

公开(公告)日：2022-07-12

申请号：US16837211

申请日：2020-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Yen Yu ,  Po-Chi Wu ,  Yueh-Chun Lai

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

摘要： In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

公开(公告)号：US11387139B2

公开(公告)日：2022-07-12

申请号：US16807448

申请日：2020-03-03

申请人： TOKYO ELECTRON LIMITED

发明人： Syuji Nozawa ,  Tatsuya Yamaguchi ,  Sunghil Lee

IPC分类号： H01L21/76 ,  H01L21/764 ,  H01L21/02 ,  H01L21/3105

摘要： A method of manufacturing a semiconductor device, the method including: a first film deposition process of stacking a polymer film on a substrate on which a recess is formed, wherein the polymer film is a film of a polymer having a urea bond and is formed by polymerizing a plurality of kinds of monomers; a second film deposition process of stacking a sealing film on the substrate in a state in which at least a bottom and a sidewall of the recess are covered with the polymer film; and a desorbing process of desorbing and diffusing the polymer film under the sealing film through the sealing film by depolymerizing the polymer film by heating the substrate to a first temperature.

公开(公告)号：US11380768B2

公开(公告)日：2022-07-05

申请号：US16886572

申请日：2020-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Cheng Chen ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/40 ,  H01L21/8238 ,  H01L23/522

摘要： A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.