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    Transistor logic output device for diversion of Miller current
    51.
    发明授权
    Transistor logic output device for diversion of Miller current 失效
    晶体管逻辑输出装置，用于切换米勒电流

    公开(公告)号：US4330723A

    公开(公告)日：1982-05-18

    申请号：US65991

    申请日：1979-08-13

    Applicant: Paul J. Griffith

    Inventor： Paul J. Griffith

    IPC: H03K19/088 ,  H03K19/013 ,  H03K5/12 ,  H03K19/084

    CPC classification number: H03K19/0136

    Abstract: A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called capacitive feedback Miller current generated during the low to high potential transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The active element discharging transistor is controlled at its base by the potential at the collector of the phase splitter element and is coupled to follow changes in voltage at the phase splitter collector for receiving base drive current during the transition from low to high potential at the device output and when the phase splitter is not conducting. The active element thereby provides a low impedance path to ground or low potential at the base of the pulldown element transistor means for diverting and discharging the capacitive Miller feedback current. When the phase splitter is conducting, the active element discharge transistor is deprived of base drive current and affords a high impedance.

    Abstract translation: 晶体管逻辑输出装置设置有耦合在下拉元件晶体管的基极和接地或低电位之间的有源元件放电晶体管，用于主动地控制到地的线路或低电位，用于转移和放电所产生的所谓的电容反馈米勒电流 在由下拉元件晶体管中的基极 - 集电极结电容引起的器件输出端的低电位到高电位转变期间。 有源元件放电晶体管在其基极处被控制在相位分离器元件的集电极处的电位，并且被耦合以跟随在分相器集电极处的电压的变化，以在器件从低电平转换到高电位期间接收基极驱动电流 当分相器不导通时。 因此，有源元件在下拉元件晶体管装置的基极处提供到地或低电位的低阻抗路径，用于转移和放电电容米勒反馈电流。 当分相器导通时，有源元件放电晶体管被剥夺基极驱动电流并提供高阻抗。

    Gate circuit
    52.
    发明授权
    Gate circuit 失效
    门电路

    公开(公告)号：US4110634A

    公开(公告)日：1978-08-29

    申请号：US712668

    申请日：1976-08-09

    Applicant: Yukuya Tokumaru ,  Masanori Nakai

    Inventor： Yukuya Tokumaru ,  Masanori Nakai

    IPC: H01L27/02 ,  H03K19/084 ,  H03K19/091 ,  H03K19/08 ,  H03K19/20

    CPC classification number: H01L27/0237 ,  H03K19/084 ,  H03K19/091

    Abstract: A gate circuit is constituted by a plurality of logical elements formed on the same P type semiconductor substrate. Each logical element is composed of an N type first region and P type second region formed by double diffusion in one of a plurality of P type isolated islands formed on a P type semiconductor substrate, and an N type isolating region and N type buried region surrounding the islands. The P type second region, N type first region and P type island constitute a first vertical PNP transistor by operating as an emitter, base and collector, respectively, while the N type first region, P type island and N type buried region constitute a second vertical NPN transistor by operating as an emitter, base and collector, respectively. In the plurality of logical elements, a Schottky diode is provided for each input section thereof. Connected to a connection point between an anode of this Schottky diode and a base of the second vertical NPN transistor of one logical element is a collector of that of another logical element. A collector of the second NPN transistor of one logical element constitutes an output section.

    Abstract translation: 门电路由形成在同一P型半导体衬底上的多个逻辑元件构成。 每个逻辑元件由形成在P型半导体衬底上的多个P型隔离岛中的一个中的双扩散形成的N型第一区和P型第二区组成，N型隔离区和N型掩埋区围绕 岛屿。 P型第二区域，N型第一区域和P型岛分别通过作为发射极，基极和集电极而构成第一垂直PNP晶体管，而N型第一区域，P型岛状物和N型掩埋区域构成第二垂直PNP晶体管 垂直NPN晶体管分别作为发射极，基极和集电极工作。 在多个逻辑元件中，为其每个输入部分提供肖特基二极管。 连接到该肖特基二极管的阳极和一个逻辑元件的第二垂直NPN晶体管的基极之间的连接点是另一个逻辑元件的集电极。 一个逻辑元件的第二NPN晶体管的集电极构成输出部分。

    High density semiconductor circuit layout
    53.
    发明授权
    High density semiconductor circuit layout 失效
    高密度半导体电路布局

    公开(公告)号：US4080720A

    公开(公告)日：1978-03-28

    申请号：US754704

    申请日：1976-12-27

    Applicant: John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

    Inventor： John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

    IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L29/72

    CPC classification number: H01L23/528 ,  H01L27/11801 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L2924/0002 ,  H01L2924/3011

    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

    Decoding system
    54.
    发明授权
    Decoding system 失效
    解码系统

    公开(公告)号：US3665460A

    公开(公告)日：1972-05-23

    申请号：US85987969

    申请日：1969-09-22

    Applicant: TOKYO SHIBAURA ELECTRIC CO

    Inventor： MURAKAMI JUNZO ,  ASAKAWA SHIGEE ,  TAKEUCHI KEIJI

    IPC: H03K17/74 ,  H03K19/082 ,  H03K19/084 ,  H03M1/00 ,  H03K13/04

    CPC classification number: H03K19/084 ,  H03K17/74 ,  H03K19/082 ,  H03M1/368 ,  H03M1/785

    Abstract: A decoding system comprising a network including a plurality of signal supply terminals respectively corresponding to individual digits in the form of binary code, a signal source generating electric signals of three different values in response to the most significant digit and each corresponding digit, said electric signals being selectively applied to the corresponding signal supply terminals by means of switching circuits.

    Abstract translation: 一种解码系统，包括：网络，包括分别对应于二进制码形式的各个数字的多个信号提供端;响应于最高有效位和每个相应数字产生三个不同值的电信号的信号源，所述电信号 通过开关电路选择性地施加到相应的信号提供端。

    Semiconductor logic circuit
    56.
    发明授权
    Semiconductor logic circuit 失效

    公开(公告)号：US3562549A

    公开(公告)日：1971-02-09

    申请号：US3562549D

    申请日：1968-05-21

    Applicant: MOLEKULARELEKTRONIK

    Inventor： TEICHMANN JUERGEN

    IPC: H03K19/084 ,  H03K19/36 ,  H03K5/08

    CPC classification number: H03K19/084

    Abstract: A plurality of diode inputs is connected through a Zener diode clipper and amplifier circuit with a subsequent output stage so that the Zener voltage determines the initial shifting voltage level. To change this initial level, a conventional negator controls a transistor connected in parallel with said clipper and amplifier circuits, and turns off the latter in dependence on the output condition.

    Control logic circuit
    57.
    发明授权
    Control logic circuit 失效
    控制逻辑电路

    公开(公告)号：US3557383A

    公开(公告)日：1971-01-19

    申请号：US3557383D

    申请日：1967-10-02

    Applicant: WESTINGHOUSE ELECTRIC CORP

    Inventor： WAVRE ANDRE ,  THOMPSON FRANCIS T ,  RUBNER TIBOR D

    IPC: H03K19/084 ,  H03K19/173 ,  H03K3/26

    CPC classification number: H03K19/1731 ,  H03K19/084

    Abstract: A universal logic gate for fabrication as an integrated circuit includes a first input section and a second input section each of which may be selectively chosen for connection to an inverting or output stage. The circuit includes a threshold means so that the response of the output stage is limited to certain signals within predetermined binary voltage ranges. In one embodiment the threshold means takes the form of a biased transistor, and in another embodiment takes the form of a voltage breakdown diode. The circuit also includes a low pass filter network to provide a time delay such that the output stage responds to the input signals only after a predetermined time delay. With fabrication as an integrated circuit, terminal connections are provided such that an external capacitor for governing the time delay may be connected.

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