公开(公告)号：UST101804I4

公开(公告)日：1982-05-04

申请号：US146909

申请日：1980-05-05

Applicant: John Balyoz ,  Algirdas J. Grwodis

Inventor： John Balyoz ,  Algirdas J. Grwodis

IPC: H01L23/528 ,  H01L27/118

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.

公开(公告)号：UST100501I4

公开(公告)日：1981-04-07

申请号：US058360

申请日：1979-07-17

Applicant: John Balyoz ,  Algirdas J. Gruodis

Inventor： John Balyoz ,  Algirdas J. Gruodis

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

CPC classification number: H01L27/11801 ,  H01L23/522 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the method for fabricating a semiconductor substrate integrated circuit layout including: forming a plurality of spaced-apart circuit cells in columnar arrays within said substrate; forming a first insulating layer above said substrate, said layer having apertures therein to expose selected active regions of said selected cells; the improvement comprising: depositing first and second sets of elongated conductors in substantially parallel relationship atop said first insulating layer in said columnar direction; said first set being disposed directly atop said exposed cells to make selected contact with selected ones of said exposed active regions through said apertures in said first insulating layer; said second set being disposed in areas between said exposed cells; forming a second insulating layer above said first and second sets of conductors, said second insulating layer having apertures therein to expose selected ones of said first and second sets; and depositing a third set of substantially parallel, elongated conductors atop said second insulating layer, orthogonally with respect to said columnar direction, to make selected contact with said exposed ones of said first and second sets through said apertures in said second insulating layer.

公开(公告)号：US4032962A

公开(公告)日：1977-06-28

申请号：US644775

申请日：1975-12-29

Applicant: John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

Inventor： John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical geometric form and arranged in columnar arrays.

Abstract translation: 一种在半导体衬底中具有新颖布局的集成逻辑电路。 衬底内的电路所需的面积显着小于现有布局的面积。 每个电路包括第一器件，其包括细长杂质区域和与细长区域处于连续关系中的一组其它杂质区域; 以形成一组二极管结。 细长区域能够容纳预定的最大数目的其它杂质区域。 第二装置位于所述第一装置的窄边附近。 第一组第一级导体在细长区域上相对于细长方向正交延伸，并且与其它杂质区域中的选定的互连件互连。 另一个导体是在衬底上方的第二层与第二器件的杂质区连接并基本上平行于细长方向延伸。 在大多数情况下，该导体将第二器件与第一组中的导体之一连接。 每个电路的参考电位连接也优选地由相同方向上运行的导电通道制成。 关于芯片架构，每个逻辑电路具有基本相同的几何形状并且以柱状阵列布置。

公开(公告)号：US4737836A

公开(公告)日：1988-04-12

申请号：US842062

申请日：1986-03-18

Applicant: Haluk O. Askin ,  Doyle E. Beaty, Jr. ,  Joseph R. Cavaliere ,  Guy Rabbat ,  John Balyoz ,  Achilles A. Sarris

Inventor： Haluk O. Askin ,  Doyle E. Beaty, Jr. ,  Joseph R. Cavaliere ,  Guy Rabbat ,  John Balyoz ,  Achilles A. Sarris

IPC: H01L23/528 ,  H01L27/118 ,  H01L27/10 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H01L2924/0002

Abstract: A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.

Abstract translation: 提供了非常大规模的多单元集成电路，其具有显着改善的电路密度。 有源和无源电路元件都使用普通扩散技术形成在半导体衬底中。 然后，优选地由多晶硅材料制成的连接器形成在基板的表面上。 连接器具有沿着预定线定位的接合焊盘区域，其中可以定位稍后形成的金属化层的金属连接器。 一些连接器具有连接到电路元件的焊盘区域，而其他连接器区域不连接。 随后形成的金属化层可以用于使用多晶硅连接器以任何期望的电路配置将各种电路元件和多个电池单元连接在一起。

公开(公告)号：US4080720A

公开(公告)日：1978-03-28

申请号：US754704

申请日：1976-12-27

Applicant: John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

Inventor： John Balyoz ,  Algirdas Joseph Gruodis ,  Teh-Sen Jen ,  Wadie Faltas Mikhail

IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L29/72

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

公开(公告)号：UST106201I4

公开(公告)日：1986-03-04

申请号：US457786

申请日：1983-01-13

Applicant: John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

Inventor： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

IPC: H01L23/528 ,  H01L27/118

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors.

公开(公告)号：US4295149A

公开(公告)日：1981-10-13

申请号：US974576

申请日：1978-12-29

Applicant: John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

Inventor： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

CPC classification number: H01L27/11801 ,  H01L23/528 ,  H01L2924/0002

Abstract: Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions.In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

Abstract translation: 公开了被称为“主映像芯片组织技术”的改进的LSI半导体设计结构。 利用该技术提供了增加的密度和优化的半导体器件，电路和部件号功能的性能。 根据所公开的主图像芯片组合方法，半导体芯片被最佳地构造以便于最大数量的器件和电路，并且有助于制造各种LSI部件号。 基本上，半导体表面都没有专用于信号和电源布线通道。 提供了主图像布线结构，其驻留在半导体表面上并在功率表面下方。 此外，主图像布线结构提供了用于个性化用于多功率表面结构的功率和信号布线的装置。 组合的主图像结构提供了用于最佳地分配设备，功能单元（微和宏）以及信号和电力布线的半导体区域以便于改进密度和性能的手段。

公开(公告)号：US4249193A

公开(公告)日：1981-02-03

申请号：US909605

申请日：1978-05-25

Applicant: John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

Inventor： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L27/11801 ,  H01L2924/0002 ,  Y10S257/923

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices.In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

Abstract translation: 公开了一种改进的主机设计技术，包括结构，布线和制造方法，以提供改进的大规模集成器件。 根据改进的主机技术，提供了多个半导体芯片，其中基本上每个芯片的整个半导体表面积用于提供可选择的个性化（有线）的单元。 半导体表面积都不用于布线通道。 如果不是全部包含在每个芯片上的单元，则可以最佳地达到单个单元面积和单元配置以便最大数量的布线，从而可以容易地制造各种LSI器件部件号，从而电路密度得到实质性改善。