公开(公告)号：US06638801B2

公开(公告)日：2003-10-28

申请号：US10106642

申请日：2002-03-26

申请人： Kazutaka Manabe

发明人： Kazutaka Manabe

IPC分类号： H01L21338

CPC分类号： H01L27/10873 ,  H01L21/28114 ,  H01L21/2815 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

公开(公告)号：US06627488B2

公开(公告)日：2003-09-30

申请号：US09891210

申请日：2001-06-26

申请人： Jung Ho Lee

发明人： Jung Ho Lee

IPC分类号： H01L21338

CPC分类号： H01L29/66477 ,  H01L21/31053 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66621

摘要： Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and planarizing an interlayer insulating film formed on the substrate to expose the dummy gate electrode; etching the dummy gate electrode to form a groove in an exposed portion of the substrate; implanting impurity ions into the exposed portion of the substrate to form a delta-doping layer; thermally treating the semiconductor substrate to activate the implanted impurity ions; growing a silicon film on the exposed portion of the substrate by a selective epitaxial process; depositing a gate insulating film on the surface of the groove; and depositing a gate metal film on the gate insulating film in the groove, forming the gate electrode.

公开(公告)号：US06620716B2

公开(公告)日：2003-09-16

申请号：US10114453

申请日：2002-04-03

申请人： Kozo Makiyama ,  Katsumi Ogiri

发明人： Kozo Makiyama ,  Katsumi Ogiri

IPC分类号： H01L21338

CPC分类号： H01L29/66462 ,  H01L21/28114 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376

摘要： A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

摘要翻译： 制造半导体器件的方法包括通过执行多个显影步骤形成具有多层结构的抗蚀剂图案，所述抗蚀剂图案包括对应于栅电极的精细栅极部分的第一开口和位于所述栅电极上的第二开口 所述第二开口对应于比所述细门部分宽的横截面部分，并且具有如悬垂突出的横截面，其中所述过门部分顶端处的所述第二开口的每个角度大于 90度; 以及通过在抗蚀剂图案上沉积电极材料来形成设置有精细栅极部分和栅极极化部分的栅电极。

公开(公告)号：US06613621B2

公开(公告)日：2003-09-02

申请号：US09803244

申请日：2001-03-09

申请人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

发明人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

IPC分类号： H01L21338

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/41783 ,  H01L29/66537 ,  H01L29/66545

摘要： Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

摘要翻译： 集成电路中的自对准触点可以形成在具有有源区的集成电路基板上。 可以在绝缘层中形成沟槽，并且可以在沟槽中形成导电材料到凹陷在凹槽中的水平。 绝缘材料可以形成在导电材料上的相对于绝缘层具有蚀刻选择性的凹槽中。 然后可以形成与活性区域自对准的接触。

公开(公告)号：US06570233B2

公开(公告)日：2003-05-27

申请号：US09901071

申请日：2001-07-10

申请人： Akira Matsumura

发明人： Akira Matsumura

IPC分类号： H01L21338

CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

摘要翻译： 本发明提供了一种用于降低直接接触电阻并减少接头泄漏同时保持穿孔余量的技术。 提供一种半导体集成电路器件，包括：衬底; 形成在基板上的晶体管，其包括源极，漏极和控制从所述源极流向所述漏极的电流的栅极; 以及接触插塞，其电连接到所述源极和漏极中的至少一个并由包括掺杂剂的导电材料制成。 接触塞由至少第一层和第二层形成。 第一层与源极和漏极中的一个接触，并且由包括第一浓度的掺杂剂的所述材料制成。 第二层由包括低于第二浓度的第二浓度的掺杂剂的所述材料层形成。

公开(公告)号：US06555424B2

公开(公告)日：2003-04-29

申请号：US09879967

申请日：2001-06-14

申请人： Horng-Chih Lin ,  Ming-Shih Tsai ,  Tiao-Yuan Huang

发明人： Horng-Chih Lin ,  Ming-Shih Tsai ,  Tiao-Yuan Huang

IPC分类号： H01L21338

CPC分类号： H01L29/458 ,  H01L29/78609 ,  H01L29/78636 ,  H01L29/78645

摘要： The present invention discloses a thin film transistor with sub-gates and Schottky source/drain and a method of manufacturing the same. Doping of source/drain, and the following annealing steps used conventionally are omitted and the complexity of process and process costs are reduced. The temperature of the process is also decreased. A thin film transistor with sub-gates and Schottky source/drain of the invention is able to operate in both the n type and p type channel modes on the same transistor element depending on the biased voltage of the sub-gate. Moreover, an electric junction is formed by induction, using bias voltage applied on the sub-gate, which takes the place of the conventional source/drain extensions. Consequently, the off-state leakage current is reduced.

公开(公告)号：US06548333B2

公开(公告)日：2003-04-15

申请号：US09904333

申请日：2001-07-12

申请人： Richard Peter Smith

发明人： Richard Peter Smith

IPC分类号： H01L21338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/7783

摘要： High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment. The gate contact extends only a portion of a distance between the first sidewall and the second sidewall of the GaN-based cap segment.

摘要翻译： 提供高电子迁移率晶体管（HEMT）和制造HEMT的方法提供根据本发明实施例的器件包括沟道层上的氮化镓（GaN）沟道层和氮化镓（AlGaN）阻挡层。 第一欧姆接触提供在阻挡层上以提供源电极，并且第二欧姆接触还设置在阻挡层上并且与源电极间隔开以提供漏电极。 在源电极和漏电极之间的阻挡层上设置GaN基帽段。 GaN基帽段具有与源电极相邻并间隔开的第一侧壁，并且可以具有与漏电极相邻并间隔开的第二侧壁。 在GaN基帽部分上提供非欧姆接触以提供栅极接触。 栅极触点具有基本上与GaN基帽段的第一侧壁对准的第一侧壁。 栅极接触仅延伸GaN基帽段的第一侧壁和第二侧壁之间的距离的一部分。

公开(公告)号：US06524901B1

公开(公告)日：2003-02-25

申请号：US10176228

申请日：2002-06-20

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L29/42376

摘要： Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sidewalls of the notched dummy gate. The dummy gate is removed, and a notched gate is formed. The methods allow the height and depth of the notches to be independently controlled, and transistors having shorter channel lengths are formed.

摘要翻译： 提供了用于形成具有凹口的栅极和半导体器件的方法。 该方法利用在衬底上形成虚拟栅极。 蚀刻虚拟栅极以在虚拟栅极中形成凹口，并且在缺口伪栅极的侧壁上形成侧壁间隔物。 去除虚拟栅极，形成有缺口的栅极。 这些方法允许独立地控制凹口的高度和深度，并且形成具有较短沟道长度的晶体管。

公开(公告)号：US06524899B1

公开(公告)日：2003-02-25

申请号：US09667360

申请日：2000-09-21

申请人： Ronald W. Grundbacher ,  Richard Lai ,  Mark Kintis ,  Michael E. Barsky ,  Roger S. Tsai

发明人： Ronald W. Grundbacher ,  Richard Lai ,  Mark Kintis ,  Michael E. Barsky ,  Roger S. Tsai

IPC分类号： H01L21338

CPC分类号： H01L29/66143 ,  H01L21/30612 ,  H01L29/66462

摘要： A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

摘要翻译： 使用柠檬酸蚀刻剂制造HEMT IC的方法。 为了通过单个蚀刻步骤形成不同尺寸的浇口，使用柠檬酸蚀刻剂，其包括柠檬酸钾，柠檬酸和过氧化氢。 首先用光致抗蚀剂旋转晶片，然后通过光学光刻将其形成图案。 将晶片浸入蚀刻剂中以蚀刻暴露的半导体材料。 将金属电极蒸发到晶片上，并用溶剂除去剩余的光致抗蚀剂。

公开(公告)号：US06458640B1

公开(公告)日：2002-10-01

申请号：US09871740

申请日：2001-06-04

申请人： Weiqi Li

发明人： Weiqi Li

IPC分类号： H01L21338

CPC分类号： H01L29/66871 ,  H01L29/1029 ,  H01L29/8128

摘要： A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.

摘要翻译： MESFET具有在源极和栅极之间延伸的第一部分中具有第一掺杂分布的导电沟道，以及在栅极和漏极之间延伸的第二部分中的第二掺杂分布。 背景p型区域设置在第一部分下方，但不一定位于第二部分之后。