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    Method and system for accelerating the conversion process between encryption schemes
    51.
    发明授权
    Method and system for accelerating the conversion process between encryption schemes 有权
    加密方案加速转换过程的方法和系统

    公开(公告)号：US07386717B2

    公开(公告)日：2008-06-10

    申请号：US10094350

    申请日：2002-03-07

    申请人： Koteshwerrao Adusumilli

    发明人： Koteshwerrao Adusumilli

    IPC分类号： H04L9/00 ,  G06F12/04

    CPC分类号： H04L63/0209 ,  H04L29/06 ,  H04L63/0464 ,  H04L63/0485 ,  H04L63/166 ,  H04L67/04 ,  H04L69/24 ,  H04L69/329 ,  H04W4/18 ,  H04W12/02 ,  H04W88/16

    摘要： A method and system is provided for accelerating the conversion process between encryption schemes. The system includes a board in a gateway. The board includes a controller to receive security parameters and data encrypted according to a first encryption scheme and control the transmission of the data. The system includes a hardware device coupled to the controller to decrypt the data and encrypt the data according to a second encryption scheme. The data is then transmitted to the controller to be forwarded out of the gateway.

    摘要翻译： 提供了加速加密方案之间的转换过程的方法和系统。 该系统包括网关中的电路板。 该板包括控制器，用于接收根据第一加密方案加密的安全参数和数据，并控制数据的传输。 该系统包括耦合到控制器的硬件设备，用于根据第二加密方案解密数据和加密数据。 然后将数据发送到控制器以从网关转发出来。

    Device and method for writing data in a processor to memory at unaligned location
    52.
    发明授权
    Device and method for writing data in a processor to memory at unaligned location 有权
    将处理器中的数据写入未对齐位置的存储器的设备和方法

    公开(公告)号：US07308556B2

    公开(公告)日：2007-12-11

    申请号：US10989408

    申请日：2004-11-17

    申请人： Bor-Sung Liang

    发明人： Bor-Sung Liang

    IPC分类号： G06F12/04

    CPC分类号： G06F5/00 ,  G06F7/76 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824

    摘要： A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the internal register for rotating data of the internal register to a first position in accordance with written unaligned address. A store combine register is coupled to the rotator for temporarily storing data of the rotator. A mask selector is coupled to the rotator and the store combine register for selectively masking their data in accordance with the written unaligned address and storing the data masked to the memory.

    摘要翻译： 用于将处理器中的数据写入未对齐位置的存储器的装置。 数据存储在处理器的内部寄存器中，用于将由字边界分隔的存储器的未对齐地址写入到多个字中。 旋转器耦合到内部寄存器，用于根据写入的未对齐地址将内部寄存器的数据旋转到第一位置。 存储组合寄存器耦合到旋转器，用于临时存储旋转器的数据。 屏蔽选择器被耦合到旋转器和存储组合寄存器，用于根据写入的未对齐地址选择性地屏蔽它们的数据，并将屏蔽的数据存储到存储器中。

    Processor-based automatic alignment device and method for data movement
    53.
    发明授权
    Processor-based automatic alignment device and method for data movement 有权
    基于处理器的自动对准装置和数据移动方法

    公开(公告)号：US07308554B2

    公开(公告)日：2007-12-11

    申请号：US10987164

    申请日：2004-11-15

    申请人： Bor-Sung Liang

    发明人： Bor-Sung Liang

    IPC分类号： G06F12/04

    CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F9/3824

    摘要： A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Then, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

    摘要翻译： 一种基于处理器的自动对准装置和数据移动方法。 存储在第一位置的存储器中的数据被字边界划分为第一部分，第二部分和第三部分，并在第二位置被写入存储器。 该器件包括：内部寄存器，负载组合寄存器，移位器，旋转器，存储组合寄存器和掩码选择器。 数据被加载并由设备对准以存储在处理器的内部寄存器中。 然后，存储在内部寄存器中的数据将自动对齐，然后以不对齐的位置写入存储器。

    Vectorized table lookup
    55.
    发明申请
    Vectorized table lookup 审中-公开

    公开(公告)号：US20060101229A1

    公开(公告)日：2006-05-11

    申请号：US11289293

    申请日：2005-11-30

    申请人： Ali Sazegari

    发明人： Ali Sazegari

    IPC分类号： G06F12/04

    CPC分类号： G06F7/764 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/345 ,  G06F16/9017

    摘要： A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask. The select mask is then used during a select operation, to choose between the results of permute instructions on different ones of the logically divided sets of data. Multi-byte table entries are retrieved by replicating each index value and adding consecutive values to form multiple consecutive index values that are then used in multiple permute operations.

    Data processor
    58.
    发明申请
    Data processor 失效
    数据处理器

    公开(公告)号：US20050268027A1

    公开(公告)日：2005-12-01

    申请号：US11130217

    申请日：2005-05-17

    申请人： Fumie Katsuki ,  Takanobu Naruse ,  Chiaki Fujii

    发明人： Fumie Katsuki ,  Takanobu Naruse ,  Chiaki Fujii

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/04 ,  G06F13/16

    CPC分类号： G06F12/0875 ,  G06F13/1678

    摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.

    摘要翻译： 当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。 该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块 与每条巴士对应。 存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。 因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中，并且在执行连续数据时使用存储的数据而不使其消失 以比外部存储器的数据总线宽度更小的数据大小读取。

    Architecture to relax memory performance requirements
    59.
    发明授权
    Architecture to relax memory performance requirements 有权
    架构放松内存性能要求

    公开(公告)号：US06970993B2

    公开(公告)日：2005-11-29

    申请号：US10658058

    申请日：2003-09-08

    申请人： Bruce L. Troutman ,  Russell B. Lloyd ,  Randal Q. Thornley

    发明人： Bruce L. Troutman ,  Russell B. Lloyd ,  Randal Q. Thornley

    IPC分类号： G06F12/04 ,  G06F12/00

    CPC分类号： G06F12/04

    摘要： The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

    摘要翻译： 本发明提供一种允许存储可变长度指令而不浪费存储空间的存储架构。 一个，两个和三个字节的指令都可以在单个提取中检索。 该示例性实施例将存储块划分成具有一些特殊寻址电路的两个x16存储器。 该结构将内存逻辑排列成四行字节列中的每一行。 对于这些x16存储器中的第一个，提供了完整的地址。 如果地址在第二x16存储器的两列内，则还将向第二x16存储器提供完整地址。 如果地址是x16存储器中的第一个，则第二x16存储器代替地接收指定行的地址部分。 这导致双行访问，最后一个或两个字节的3字节指令由第一个字节之上的行提供。 最终的效果是所有的物理内存物理空间都用于程序代码，24位访问中没有浪费。

    Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
    60.
    发明申请
    Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner 有权

    公开(公告)号：US20050262288A1

    公开(公告)日：2005-11-24

    申请号：US11121172

    申请日：2005-05-04

    申请人： Graham Kirsch

    发明人： Graham Kirsch

    IPC分类号： G06F15/16 ,  G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G06F15/80

    CPC分类号： G06F15/8007 ,  G06F15/7821

    摘要： A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word. The selection is achieved utilizing a multiplexer on the input to the register and a pair of tri-state drivers which drive each data line.