公开(公告)号：US08968006B1

公开(公告)日：2015-03-03

申请号：US13944610

申请日：2013-07-17

Applicant: Metrospec Technology, L.L.C.

Inventor： Henry V. Holec ,  Wm. Todd Crandell

IPC: H01R12/00 ,  H05K1/14 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0293 ,  F21Y2107/30 ,  F21Y2115/10 ,  H01R4/02 ,  H01R9/096 ,  H01R12/523 ,  H01R13/717 ,  H05K1/0266 ,  H05K1/0269 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/118 ,  H05K1/14 ,  H05K1/144 ,  H05K1/147 ,  H05K3/0061 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09918 ,  H05K2201/10106 ,  H05K2201/2027 ,  H05K2203/0228

Abstract: In some embodiments, an interconnectable circuit board may include one or more of the following features: (a) a first electrically conductive pad located on a top of the circuit board, (b) a plated through hole on the conductive pad which passes through the circuit board, (c) a second electrically conductive pad coupled to the plated through hole; the second conductive pad capable of being electrically connected to a third electrically conductive pad attached to a top of a second interconnectable circuit board, (d) cut marks indicating safe locations for separating the circuit board, and (e) a second cut mark adjacent to the first cut mark where the area between the first and second cut mark can be utilized to make a safe cut through the circuit board.

Abstract translation: 在一些实施例中，可互连电路板可以包括以下特征中的一个或多个：（a）位于电路板顶部的第一导电焊盘，（b）导电焊盘上的电镀通孔， 电路板，（c）耦合到电镀通孔的第二导电焊盘; 第二导电焊盘能够电连接到附接到第二可互连电路板的顶部的第三导电焊盘，（d）切割标记，指示用于分离电路板的安全位置，以及（e）与第二导电焊盘相邻的第二切割标记 可以利用第一和第二切割标记之间的区域来进行通过电路板的安全切割的第一切割标记。

公开(公告)号：US20150008571A1

公开(公告)日：2015-01-08

申请号：US13937040

申请日：2013-07-08

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd

Inventor： Adam Gallegos ,  Walter J. Dauksher

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/06

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10155 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/26155 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83007 ,  H01L2224/83203 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/041 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.

Abstract translation: 公开了一种芯片封装及其制造方法。 特别地，公开了一种包括球栅阵列的芯片封装，其中芯片封装包括支撑球栅阵列的封装衬底，其中芯片封装还包括翘曲控制框架，其帮助最小化或减轻芯片封装的翘曲 。

公开(公告)号：US20140376199A1

公开(公告)日：2014-12-25

申请号：US14480767

申请日：2014-09-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO ,  Masahiro OZAWA ,  Satoshi ISHINO ,  Jun SASAKI

IPC: H05K1/14 ,  H05K7/14 ,  H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/144 ,  H01P3/08 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/11 ,  H05K7/1427 ,  H05K2201/0195 ,  H05K2201/041

Abstract: A laminate body includes a plurality of dielectric sheets laminated together. A first ground conductor is provided in or on the laminate body. A second ground conductor is provided in or on the laminate body and located on a different layer from the first ground conductor. A signal line is provided between the ground conductors and with respect to a direction of lamination. A signal line is provided between the ground conductors and with respect to the direction of lamination and located closer to the second ground conductor than the signal line is, and the signal line has a portion extending along the signal line in a parallel-lines area when viewed from the direction of lamination. The first ground conductor has openings in the parallel-lines area, and the openings are arranged over the signal line when viewed from the direction of lamination.

Abstract translation: 层压体包括层叠在一起的多个电介质片。 第一接地导体设置在层压体上或其上。 第二接地导体设置在层压体上或其上并且位于与第一接地导体不同的层上。 在接地导体之间并相对于层压方向设置信号线。 在接地导体之间并且相对于层叠方向设置信号线，并且比信号线更靠近第二接地导体，并且信号线具有沿着平行线区域中的信号线延伸的部分， 从层压方向看。 第一接地导体在平行线区域中具有开口，并且当从层压方向观察时，开口布置在信号线上方。

公开(公告)号：US20140185226A1

公开(公告)日：2014-07-03

申请号：US13730505

申请日：2012-12-28

Applicant: Hue V. Lam ,  Loc V. Doan

Inventor： Hue V. Lam ,  Loc V. Doan

IPC: G06F1/16

CPC classification number: H05K1/141 ,  G06F21/86 ,  G11C5/04 ,  H05K1/117 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10098 ,  H05K2201/10159 ,  H05K2201/10409

Abstract: Embodiments of the invention describe a motherboard PCB having a memory bus to receive signal data from a channel of memory chips/devices of a memory module. Electrical contacts, communicatively coupled to the memory bus, securely couple the PCB to the memory chips/devices of the memory module. Embodiments of the invention further include a receiving housing that includes said electrical contacts and has a height less or equal to the height of the memory module.Embodiments of the invention further describe a memory module having a memory card housing, first and second pluralities of memory chips/devices included in the housing, and first and second pluralities of memory module electrical I/O terminals for coupling the first and second pluralities of memory chips/devices to PCB, respectively. In embodiments of the invention, the above described first and second pluralities electrical I/O connectors are disposed on different sides of the housing.

Abstract translation: 本发明的实施例描述了具有存储器总线以从存储器模块的存储器芯片/器件的通道接收信号数据的母板PCB。 通信地耦合到存储器总线的电触点将PCB牢固地耦合到存储器模块的存储器芯片/器件。 本发明的实施例还包括容纳壳体，其包括所述电触头并且具有小于或等于存储器模块的高度的高度。 本发明的实施例进一步描述了具有存储卡外壳，包括在外壳中的第一和第二多个存储器芯片/器件的存储器模块，以及用于将第一和第二多个 内存芯片/器件分别到PCB。 在本发明的实施例中，上述第一和第二多个电I / O连接器设置在壳体的不同侧。

公开(公告)号：US20130329378A1

公开(公告)日：2013-12-12

申请号：US13869010

申请日：2013-04-23

Applicant: GERARD TECHNOLOGIES (SUZHOU) CO., LTD.

Inventor： Jian-Fei Hou ,  Jian Xu

IPC: H05K7/00 ,  H05K3/36 ,  H05K3/34

CPC classification number: H05K7/00 ,  H05K1/117 ,  H05K1/144 ,  H05K1/181 ,  H05K3/284 ,  H05K3/34 ,  H05K3/36 ,  H05K2201/0338 ,  H05K2201/041 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10075 ,  H05K2201/10159 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: A Universal Serial Bus device includes a PCB module, a plastic package shell and a power module. The PCB module includes a PCB, and a storage chip and a control chip both arranged on the PCB module. The PCB includes opposite front end and rear end, and opposite upper surface and lower surface. The upper surface has a number of contacting portions, and the storage chip and the control chip being arranged on the lower surface. The plastic package shell at least encapsulates the lower surface of the PCB to encapsulate the storage chip and the control chip. The power module is electrically connected to the part of the PCB module where is not encapsulated by the plastic package shell.

Abstract translation: 通用串行总线设备包括PCB模块，塑料封装外壳和电源模块。 PCB模块包括PCB，以及布置在PCB模块上的存储芯片和控制芯片。 PCB包括相对的前端和后端，以及相对的上表面和下表面。 上表面具有多个接触部分，并且存储芯片和控制芯片布置在下表面上。 塑料封装外壳至少封装PCB的下表面以封装存储芯片和控制芯片。 电源模块电连接到PCB模块的未被塑料封装外壳封装的部分。

公开(公告)号：US08274792B2

公开(公告)日：2012-09-25

申请号：US12066003

申请日：2006-09-06

Applicant: Aviv Soffer

Inventor： Aviv Soffer

IPC: H05K7/20

CPC classification number: G06F1/18 ,  F28D15/0266 ,  F28D15/0275 ,  G06F1/20 ,  G06F2200/1635 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19105 ,  H05K1/0284 ,  H05K1/185 ,  H05K7/205 ,  H05K2201/041 ,  H01L2924/00

Abstract: A 3-Dimensional multi-layered modular computer (3DMC) is disclosed that comprises removable layers of at least one CPU layer, at least one volatile memory layer, and at least one Input/Output (I/O) interface layers. The layers are stacked in parallel and are electrically connected to create a computing apparatus. Each of the layers is formed from encapsulating material having one or more internal cavities for chip dice, passive components, active components, and conductor's traces. A plurality of Thermal Conducting Rods (TCRs) is capable of conducting and removing heat generated by the components in the layers from the 3DMC apparatus to an external medium. Each TCR perpendicularly passes through the layers.

Abstract translation: 公开了一种三维多层模块化计算机（3DMC），其包括至少一个CPU层，至少一个易失性存储器层以及至少一个输入/输出（I / O）接口层的可移除层。 这些层被并联堆叠并且电连接以产生计算装置。 每个层由具有一个或多个用于芯片骰子，无源元件，有源元件和导体迹线的一个或多个内部空腔的封装材料形成。 多个导热棒（TCR）能够将来自3DMC装置的层中的组分产生的热量导出和移除到外部介质。 每个TCR垂直地穿过层。

公开(公告)号：US20120088376A1

公开(公告)日：2012-04-12

申请号：US13326845

申请日：2011-12-15

Applicant: David J. BRAUN ,  Mark G. CLARK ,  John R. DANGLER ,  Matthew S. DOYLE ,  Thomas D. KIDD ,  Jason T. STOLL

Inventor： David J. BRAUN ,  Mark G. CLARK ,  John R. DANGLER ,  Matthew S. DOYLE ,  Thomas D. KIDD ,  Jason T. STOLL

IPC: H01R12/71 ,  H01R43/00

CPC classification number: H01R43/01 ,  H01R12/52 ,  H01R12/613 ,  H01R12/778 ,  H01R12/79 ,  H05K1/0219 ,  H05K1/118 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3447 ,  H05K3/36 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/058 ,  H05K2201/09181 ,  H05K2201/09618 ,  H05K2201/10189 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/4922

Abstract: A cable assembly for interconnecting a plurality of circuit boards together by using a connector assembly connected to each of the circuit boards. The cable assembly includes a first cable having a first end part and a second cable having a second end part. A first periphery of the first end part has a plurality of first half vias that collectively form a column along a width direction of the connector assembly. A second periphery of the second end part has a plurality of second half vias that collectively form a column along the width direction of the connector assembly. The first and second end parts are coupled together to form a connecting unit, such that the first half vias and the second half vias are joined together to form full vias.

Abstract translation: 一种电缆组件，用于通过连接到每个电路板的连接器组件将多个电路板互连在一起。 电缆组件包括具有第一端部的第一电缆和具有第二端部的第二电缆。 第一端部的第一周边具有沿着连接器组件的宽度方向共同形成列的多个第一半通孔。 第二端部的第二周边具有沿着连接器组件的宽度方向共同形成列的多个第二半通孔。 第一和第二端部联接在一起以形成连接单元，使得第一半通孔和第二半通孔连接在一起以形成完整的通孔。

公开(公告)号：US20120064670A1

公开(公告)日：2012-03-15

申请号：US13302725

申请日：2011-11-22

Applicant: Tyler Mueller ,  Geoffrey Batchelder ,  Ralph B. Danzl ,  Paul F. Gerrish ,  Anna J. Malin ,  Trevor D. Marrott ,  Michael F. Mattes

Inventor： Tyler Mueller ,  Geoffrey Batchelder ,  Ralph B. Danzl ,  Paul F. Gerrish ,  Anna J. Malin ,  Trevor D. Marrott ,  Michael F. Mattes

IPC: H01L21/52

CPC classification number: H05K1/144 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/818 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/11 ,  H05K2201/041 ,  Y10T29/49117 ,  Y10T29/49147 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Abstract translation: 保护电路免受水分侵入的装置和方法，例如使用金属结构作为湿气入口屏障的一部分。

公开(公告)号：US08125058B2

公开(公告)日：2012-02-28

申请号：US12569525

申请日：2009-09-29

Applicant: Tyler Mueller ,  Larry E. Tyler ,  Geoffrey Batchelder ,  Paul F. Gerrish ,  Michael F. Mattes ,  Anna J. Malin

Inventor： Tyler Mueller ,  Larry E. Tyler ,  Geoffrey Batchelder ,  Paul F. Gerrish ,  Michael F. Mattes ,  Anna J. Malin

IPC: H01L23/552

CPC classification number: H05K1/144 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/818 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/11 ,  H05K2201/041 ,  Y10T29/49117 ,  Y10T29/49147 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device. For example, the first Faraday cage portion may include a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, and a second Faraday cage portion may include a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device. Further, for example, the first Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the first conductive portion of the Faraday cage enclosure the second Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the second conductive portion of the Faraday cage enclosure. An electrical connection may be provided between the conductive contact portions of the first and second Faraday cage portions.

Abstract translation: 一种装置和方法使用第一法拉第笼部分和第二法拉第笼部分来提供围绕至少一个电路装置的法拉第笼壳。 例如，第一法拉第笼部分可以包括围绕至少一个电路装置的法拉第笼壳体的第一导电部分，并且第二法拉第笼部分可以包括围绕至少一个电路的法拉第笼壳体的第二导电部分 设备。 此外，例如，第一法拉第笼部分可以包括具有端接法拉第笼壳体的第一导电部分的一个或多个导电接触部分的连接表面，第二法拉第笼部分可以包括具有一个或多个导电接触部分终止的连接表面 法拉第笼壳的第二个导电部分。 可以在第一和第二法拉第笼部分的导电接触部分之间提供电连接。

公开(公告)号：US08106300B2

公开(公告)日：2012-01-31

申请号：US12244216

申请日：2008-10-02

Applicant: David J. Braun ,  Mark G. Clark ,  John R. Dangler ,  Matthew S. Doyle ,  Thomas D. Kidd ,  Jason T. Stoll

Inventor： David J. Braun ,  Mark G. Clark ,  John R. Dangler ,  Matthew S. Doyle ,  Thomas D. Kidd ,  Jason T. Stoll

IPC: H01B7/08

CPC classification number: H01R43/01 ,  H01R12/52 ,  H01R12/613 ,  H01R12/778 ,  H01R12/79 ,  H05K1/0219 ,  H05K1/118 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3447 ,  H05K3/36 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/058 ,  H05K2201/09181 ,  H05K2201/09618 ,  H05K2201/10189 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/4922

Abstract: A cable assembly for interconnecting a plurality of circuit boards together by using a connector assembly connected to each of the circuit boards. The cable assembly includes a first cable having a first end part and a second cable having a second end part. A first periphery of the first end part has a plurality of first half vias that collectively form a column along a width direction of the connector assembly. A second periphery of the second end part has a plurality of second half vias that collectively form a column along the width direction of the connector assembly. The first and second end parts are coupled together to form a connecting unit, such that the first half vias and the second half vias are joined together to form full vias.

Abstract translation: 一种电缆组件，用于通过连接到每个电路板的连接器组件将多个电路板互连在一起。 电缆组件包括具有第一端部的第一电缆和具有第二端部的第二电缆。 第一端部的第一周边具有沿连接器组件的宽度方向共同形成列的多个第一半通孔。 第二端部的第二周边具有沿着连接器组件的宽度方向共同形成列的多个第二半通孔。 第一和第二端部联接在一起以形成连接单元，使得第一半通孔和第二半通孔连接在一起以形成完整的通孔。