公开(公告)号：US20170207224A1

公开(公告)日：2017-07-20

申请号：US15478037

申请日：2017-04-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L27/10823 ,  H01L21/265 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

公开(公告)号：US09634134B2

公开(公告)日：2017-04-25

申请号：US14465578

申请日：2014-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10823 ,  H01L21/265 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

公开(公告)号：US09286979B2

公开(公告)日：2016-03-15

申请号：US14697849

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C11/21 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.

公开(公告)号：US20150235698A1

公开(公告)日：2015-08-20

申请号：US14697849

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY., LTD.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/21 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.

Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）结构。 RRAM结构包括在基板上的底部电极; 底部电极上的电阻材料层，电阻材料层具有长丝特征，细丝比率大于约0.5; 和电阻材料层上的顶部电极。

公开(公告)号：US20140177318A1

公开(公告)日：2014-06-26

申请号：US13725733

申请日：2012-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0045 ,  G11C2213/74

Abstract: A two-switch hybrid memory cell device includes a storage node connected between one terminal of a first switch and a gate of a second switch. The device also includes a resistive switching device connected to the storage node. The resistive switching device is to act as a capacitance by being set to a high resistive state when the memory cell is in a dynamic mode.

Abstract translation: 双开关混合存储单元装置包括连接在第一开关的一个端子和第二开关的栅极之间的存储节点。 该设备还包括连接到存储节点的电阻式交换设备。 当存储器单元处于动态模式时，电阻性开关器件通过被设置为高电阻状态而用作电容。