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    Memory Array Including Epitaxial Source Lines and Bit Lines
    51.
    发明申请
    Memory Array Including Epitaxial Source Lines and Bit Lines 有权

    公开(公告)号：US20220384484A1

    公开(公告)日：2022-12-01

    申请号：US17884348

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H01L27/11597 ,  H01L29/06 ,  H01L27/11587

    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

    Semiconductor Device and Method
    52.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20220359655A1

    公开(公告)日：2022-11-10

    申请号：US17869414

    申请日：2022-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

    FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME
    56.
    发明申请
    FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210375933A1

    公开(公告)日：2021-12-02

    申请号：US17117570

    申请日：2020-12-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L21/02

    Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

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