Abstract:
An integrated ultraviolet analyzer is described. The integrated ultraviolet analyzer can include one or more ultraviolet analyzer cells, each of which includes one or more ultraviolet photodetectors and one or more solid state light sources, which are monolithically integrated. The solid state light source can be operated to emit ultraviolet light, at least some of which passes through an analyzer active gap and irradiates a light sensing surface of the ultraviolet photodetector. A medium to be evaluated can be present in the analyzer active gap and affect the ultraviolet light as it passes there through, thereby altering an effect of the ultraviolet light on a ultraviolet photodetector.
Abstract:
A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
Abstract:
A solid-state light source (SSLS) with light modulation control is described. A SSLS device can include a main p-n junction region configured for recombination of electron-hole pairs for light emission. A supplementary p-n junction region is proximate the main p-n junction region to supplement the recombination of electron-hole pairs, wherein the supplementary p-n junction region has a smaller electron-hole life time than the electron-hole life time of the main p-n junction region. The main p-n junction region and the supplementary p-n junction region operate cooperatively in a light emission state and a light turn-off-state. In one embodiment, the recombination of electron-hole pairs occurs in the main p-n junction region during a light emission state, and the recombination of electron-hole pairs occurs in the supplementary p-n junction region light during the light turn off-state.
Abstract:
A semiconductor device including a device channel with a gate-drain region having a carrier concentration that varies laterally along a direction from the gate contact to the drain contact is provided. Lateral variation of the carrier concentration can be implemented by laterally varying one or more attributes of one or more layers located in the gate-drain region of the device.
Abstract:
A solid-state light source (SSLS) with an integrated short-circuit protection approach is described. A device can include a SSLS having an n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A field-effect transistor (FET) can be monolithically connected in series with the SSLS. The FET can have a saturation current that is greater than the normal operating current of the SSLS and less than a predetermined protection current threshold specified to protect the SSLS and the FET.
Abstract:
A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the semiconductor structure below the gate contact. Furthermore, a perforation in the plurality of perforations can extend into the semiconductor structure beyond a location of the semiconductor channel.
Abstract:
A lateral semiconductor device and/or design including a space-charge generating layer and a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
Abstract:
A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
Abstract:
A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.
Abstract:
A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.