公开(公告)号：US20190332943A1

公开(公告)日：2019-10-31

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

公开(公告)号：US20190154493A1

公开(公告)日：2019-05-23

申请号：US15886753

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G01G23/38 ,  G11C7/10 ,  G06G7/16 ,  G11C13/00

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

公开(公告)号：US20190148502A1

公开(公告)日：2019-05-16

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20190148298A1

公开(公告)日：2019-05-16

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L23/535 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US09966137B2

公开(公告)日：2018-05-08

申请号：US15343182

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/54 ,  G11C11/56 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/00

Abstract: A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The sources and drains of the field effect transistors are connected in series. A plurality of input terminals for receiving a plurality of input voltages may be connected to a drain terminal of a corresponding field effect transistor. The threshold voltages of the field effect transistors can be programmed by increasing or decreasing a number of excess minority carriers in the confined channels, thereby programming the resistance presented by the field effect transistor.

公开(公告)号：US20170271474A1

公开(公告)日：2017-09-21

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1−xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1−xA, wherein x is not 0.53.

公开(公告)号：US20240256848A1

公开(公告)日：2024-08-01

申请号：US18632180

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US11727258B2

公开(公告)日：2023-08-15

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: G06N3/063 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78391

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20230206053A1

公开(公告)日：2023-06-29

申请号：US18111471

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L29/808 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/8083 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/42324 ,  H01L29/40114 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US20230004789A1

公开(公告)日：2023-01-05

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.